Info: *******************************************************************
Info: Running Quartus Prime IP Generation Tool
	Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
	Info: Processing started: Sun Oct 28 08:58:25 2018
Info: Command: quartus_ipgenerate qts_pcie_sfp -c qts_pcie_sfp --run_default_mode_op
Info: Using INI file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/quartus.ini
Info: Found 39 IP file(s) in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test.qsys was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system.qsys was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test.qsys was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys.qsys was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_freq_counter_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_checker_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_clk_50.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_mm_bridge_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_default_pma_settings_conf_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_100.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_50.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1c_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1d_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1c_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1d.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1c.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_100.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_50.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_st_converter_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_pll_locked_interconnect_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_nativePHY_loopback_cont_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_mm_bridge_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_default_pma_settings_conf_0.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_100.ip was found in the project.
	Info: IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_50.ip was found in the project.
Info: Finished generating IP file(s) in the project.
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_freq_counter_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_freq_counter_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_checker_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_checker_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_clk_50).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_clk_50.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_mm_bridge_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_mm_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_default_pma_settings_conf_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_default_pma_settings_conf_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_100).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_100.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_50).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_clk_50.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1c_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1c_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1d_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1d_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1c_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1c_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1d).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1d.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1c).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clock_bridge_1c.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_100).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_100.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_50).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_clk_50.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_st_converter_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_st_converter_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_pll_locked_interconnect_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_pll_locked_interconnect_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_nativePHY_loopback_cont_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_nativePHY_loopback_cont_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_mm_bridge_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_mm_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_default_pma_settings_conf_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_default_pma_settings_conf_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_100).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_100.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_50).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_clk_50.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings
	Info: Peak virtual memory: 4726 megabytes
	Info: Processing ended: Sun Oct 28 08:58:26 2018
	Info: Elapsed time: 00:00:01
	Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus Prime Synthesis
	Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
	Info: Processing started: Sun Oct 28 08:58:28 2018
Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off qts_pcie_sfp -c qts_pcie_sfp
Info: Using INI file D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/quartus.ini
Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis...
Info: Project = "qts_pcie_sfp"
Info: Revision = "qts_pcie_sfp"
Info: Analyzing source files
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_reset_controller_180/synth/altera_reset_controller.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_reset_controller_180/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_handshake_clock_crosser.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_handshake_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_clock_crosser.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_avalon_st_handshake_clock_crosser_180/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_reset_controller_180/synth/altera_reset_controller.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/q_sys/altera_reset_controller_180/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_translator_180/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_translator_180/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_master_agent_180/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_slave_agent_180/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_traffic_limiter_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_merlin_multiplexer_180/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_handshake_clock_crosser.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_handshake_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_clock_crosser.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/altera_avalon_st_handshake_clock_crosser_180/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_reset_controller_180/synth/altera_reset_controller.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/altera_reset_controller_180/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_mm_bridge_0/altera_avalon_mm_bridge_180/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0/altera_avalon_mm_bridge_180/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/twentynm_xcvr_avmm.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/twentynm_xcvr_avmm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_arbiter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_arbiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/a10_avmm_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/a10_avmm_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/altera_xcvr_native_a10_functions_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/altera_xcvr_native_a10_functions_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_arb.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_arb.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/a10_xcvr_atx_pll.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/a10_xcvr_atx_pll.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_pll_embedded_debug.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_pll_embedded_debug.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_pll_avmm_csr.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_pll_avmm_csr.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/plain_files.txt" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1c_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1d_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_locked_interconnect_1c_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_avalon_sc_fifo_180/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0/altera_reset_controller_180/synth/altera_reset_controller.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_master_0/altera_reset_controller_180/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/altera_reset_controller_180/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/altera_xcvr_functions.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/altera_xcvr_functions.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/altera_xcvr_reset_control.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/altera_xcvr_reset_control.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/alt_xcvr_reset_counter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/alt_xcvr_reset_counter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/plain_files.txt" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_reset_control_0/altera_xcvr_reset_control_180/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_arbiter.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_arbiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_pcs.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_pcs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_pma.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_pma.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_xcvr_avmm.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_xcvr_avmm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_xcvr_native.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/twentynm_xcvr_native.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_a10_functions_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_a10_functions_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/a10_avmm_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/a10_avmm_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_pipe_retry.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_pipe_retry.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_avmm_csr.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_avmm_csr.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_prbs_accum.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_prbs_accum.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_odi_accel.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_odi_accel.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_arb.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_arb.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_a10_false_paths.sdc" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_a10_false_paths.sdc" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_pcie_dfe_params_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_pcie_dfe_params_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_commands_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_commands_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_functions_h.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_functions_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_program.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_program.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_cpu.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_cpu.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_master.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/pcie_mgmt_master.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_pcie_dfe_ip.sv" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/altera_xcvr_native_pcie_dfe_ip.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/plain_files.txt" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_mm_bridge_0/altera_avalon_mm_bridge_180/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0/altera_avalon_mm_bridge_180/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_default_pma_settings_conf_0/default_pma_settings_conf_10/synth/default_pma_settings_conf.v" is a duplicate of already analyzed file "D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_default_pma_settings_conf_0/default_pma_settings_conf_10/synth/default_pma_settings_conf.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Error (13225): Can't open VHDL or Verilog HDL file "ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/altera_avalon_data_pattern_generator_180/synth/xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a.v"
Error (13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/altera_avalon_data_pattern_generator_180/synth/xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a.v'
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(12): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 12
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(13): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 13
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(20): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 20
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(21): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 21
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(28): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 28
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(29): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 29
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(36): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 36
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(37): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 37
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(44): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 44
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(45): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 45
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(52): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 52
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(53): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 53
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(60): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 60
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(61): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 61
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(68): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 68
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(69): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 69
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(78): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 78
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(79): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 79
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(80): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 80
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(81): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 81
Warning (16749): Verilog HDL warning at xcvr_st_converter.v(82): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_st_converter_0/xcvr_st_converter_10/synth/xcvr_st_converter.v Line: 82
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(6): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 6
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(7): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 7
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(8): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 8
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(9): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 9
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(10): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 10
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(11): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 11
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(12): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 12
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(13): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 13
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(14): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 14
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(15): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 15
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(16): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 16
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(17): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 17
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(18): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 18
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(19): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 19
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(20): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 20
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(21): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 21
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(22): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 22
Warning (16749): Verilog HDL warning at pll_locked_interconnect.v(23): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_pll_locked_interconnect_0/pll_locked_interconnect_10/synth/pll_locked_interconnect.v Line: 23
Warning (16749): Verilog HDL warning at nativePHY_loopback_cont.v(46): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v Line: 46
Warning (16749): Verilog HDL warning at nativePHY_loopback_cont.v(47): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v Line: 47
Warning (16749): Verilog HDL warning at nativePHY_loopback_cont.v(48): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v Line: 48
Warning (16749): Verilog HDL warning at nativePHY_loopback_cont.v(49): identifier NUM_OF_CH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v Line: 49
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(6): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 6
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(7): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 7
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(8): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 8
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(9): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 9
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(10): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 10
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(11): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 11
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(12): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 12
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(13): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 13
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(14): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 14
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(15): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 15
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(16): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 16
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(17): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 17
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(18): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 18
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(19): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 19
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(20): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 20
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(21): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 21
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(22): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 22
Warning (16749): Verilog HDL warning at pll_powerdown_interconnect.v(23): identifier DATAWIDTH is used before its declaration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_pll_powerdown_interconnect_1d_0/pll_powerdown_interconnect_10/synth/pll_powerdown_interconnect.v Line: 23
Info: Elaborating from top-level entity "qts_pcie_sfp"
Info (18235): Library search order is as follows: "altera_merlin_master_translator_180; altera_merlin_slave_translator_180; altera_merlin_master_agent_180; altera_merlin_slave_agent_180; altera_avalon_sc_fifo_180; altera_merlin_router_180; altera_merlin_traffic_limiter_180; altera_merlin_demultiplexer_180; altera_merlin_multiplexer_180; altera_avalon_st_pipeline_stage_180; altera_mm_interconnect_180; altera_reset_controller_180; xcvr_test_system; altera_avalon_st_handshake_clock_crosser_180; sfp_xcvr_test; q_sys; pcie_xcvr_test; altera_avalon_mm_bridge_180; xcvr_test_system_mm_bridge_0; freq_counter_10; xcvr_test_system_freq_counter_0; altera_avalon_data_pattern_generator_core_180; xcvr_test_system_data_pattern_generator_0; altera_avalon_data_pattern_checker_core_180; altera_avalon_data_pattern_checker_180; xcvr_test_system_data_pattern_checker_0; xcvr_test_system_clk_50; xcvr_st_converter_10; sfp_xcvr_test_xcvr_st_converter_0; altera_xcvr_reset_control_180; sfp_xcvr_test_xcvr_reset_control_0; altera_xcvr_native_a10_180; sfp_xcvr_test_xcvr_native_c10_0; pll_locked_interconnect_10; sfp_xcvr_test_pll_locked_interconnect_0; nativePHY_loopback_cont_10; sfp_xcvr_test_nativePHY_loopback_cont_0; sfp_xcvr_test_mm_bridge_0; default_pma_settings_conf_10; sfp_xcvr_test_default_pma_settings_conf_0; sfp_xcvr_test_clk_100; sfp_xcvr_test_clk_50; altera_xcvr_atx_pll_a10_180; q_sys_xcvr_atx_pll_c10_1d; q_sys_xcvr_atx_pll_c10_1c; q_sys_product_info_0; pll_powerdown_interconnect_10; q_sys_pll_powerdown_interconnect_1d_0; q_sys_pll_powerdown_interconnect_1c_0; q_sys_pll_locked_interconnect_1d_0; q_sys_pll_locked_interconnect_1c_0; altera_jtag_dc_streaming_180; timing_adapter_180; altera_avalon_st_bytes_to_packets_180; altera_avalon_st_packets_to_bytes_180; altera_avalon_packets_to_master_180; channel_adapter_180; altera_jtag_avalon_master_180; q_sys_master_0; q_sys_clock_bridge_1d; q_sys_clock_bridge_1c; q_sys_clk_100; q_sys_clk_50; pcie_xcvr_test_xcvr_st_converter_0; pcie_xcvr_test_xcvr_reset_control_0; pcie_xcvr_test_xcvr_native_c10_0; pcie_xcvr_test_pll_locked_interconnect_0; pcie_xcvr_test_nativePHY_loopback_cont_0; pcie_xcvr_test_mm_bridge_0; pcie_xcvr_test_default_pma_settings_conf_0; pcie_xcvr_test_clk_100; pcie_xcvr_test_clk_50; product_info_10". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.
Info (16821): Verilog HDL info at sld_virtual_jtag_basic.v(414): going to vhdl side to elaborate module sld_jtag_endpoint_adapter File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 414
Info (19337): VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity "sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index="YES",sld_node_info_internal=203451904)(1,3)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 96
Info (17560): VHDL info at sld_jtag_endpoint_adapter.vhd(305): going to verilog side to elaborate module sld_jtag_endpoint_adapter_impl File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 305
Info (16821): Verilog HDL info at sld_jtag_endpoint_adapter_impl.sv(118): going to vhdl side to elaborate module altera_sld_agent_endpoint File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv Line: 118
Info (19337): VHDL info at altera_sld_agent_endpoint.vhd(120): executing entity "altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd Line: 120
Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=5,receive_width=26,settings="{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host { } psig 9b67919e}")(1,127)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
Info (16822): Verilog HDL info at sld_jtag_endpoint_adapter_impl.sv(118): back to verilog to continue elaboration File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv Line: 118
Info (17561): VHDL info at sld_jtag_endpoint_adapter.vhd(305): back to vhdl to continue elaboration File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 305
Info (16822): Verilog HDL info at sld_virtual_jtag_basic.v(414): back to verilog to continue elaboration File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 414
Info (16821): Verilog HDL info at q_sys_product_info_0.v(22): going to vhdl side to elaborate module product_info File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0/synth/q_sys_product_info_0.v Line: 22
Info (19337): VHDL info at product_info.vhd(7): executing entity "product_info" with architecture "rtl" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0/product_info_10/synth/product_info.vhd Line: 7
Info (16822): Verilog HDL info at q_sys_product_info_0.v(22): back to verilog to continue elaboration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_product_info_0/synth/q_sys_product_info_0.v Line: 22
Info (16821): Verilog HDL info at alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv(252): going to vhdl side to elaborate module altera_debug_master_endpoint File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv Line: 252
Info (19337): VHDL info at altera_debug_master_endpoint.vhd(120): executing entity "altera_debug_master_endpoint(addr_width=11,has_rdv=0,slave_map="{typeName altera_xcvr_atx_pll_a10 address 0x0 span 8192 hpath {} assignments {device_revision 20nm1}}")(1,101)(1,1)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_debug_master_endpoint.vhd Line: 120
Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=35,receive_width=45,num_clocks=1,settings="{fabric mapped dir agent addr_width 11 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_a10 address 0x0 span 8192 hpath {} assignments {device_revision 20nm1}}} prefer_host { } clock_rate_clk 0 psig b6c1a030}")(1,224)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
Info (16822): Verilog HDL info at alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv(252): back to verilog to continue elaboration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv Line: 252
Warning (16788): Net "rcfg_emb_strm_chan_sel[0]" does not have a driver at alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv(110) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv Line: 110
Warning (16788): Net "g_jtag.jtag_readdatavalid" does not have a driver at alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv(215) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1c/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_fv65zbq.sv Line: 215
Info (16821): Verilog HDL info at alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv(252): going to vhdl side to elaborate module altera_debug_master_endpoint File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv Line: 252
Info (16822): Verilog HDL info at alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv(252): back to verilog to continue elaboration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv Line: 252
Warning (16788): Net "rcfg_emb_strm_chan_sel[0]" does not have a driver at alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv(110) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv Line: 110
Warning (16788): Net "g_jtag.jtag_readdatavalid" does not have a driver at alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv(215) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/q_sys/q_sys_xcvr_atx_pll_c10_1d/altera_xcvr_atx_pll_a10_180/synth/alt_xcvr_atx_pll_rcfg_opt_logic_bgzdfsa.sv Line: 215
Warning (13469): Verilog HDL assignment warning at nativePHY_loopback_cont.v(73): truncated value with size 32 to match size of target (1) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_nativePHY_loopback_cont_0/nativePHY_loopback_cont_10/synth/nativePHY_loopback_cont.v Line: 73
Warning (13469): Verilog HDL assignment warning at default_pma_settings_conf.v(116): truncated value with size 10 to match size of target (9) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_default_pma_settings_conf_0/default_pma_settings_conf_10/synth/default_pma_settings_conf.v Line: 116
Info (16821): Verilog HDL info at alt_xcvr_native_rcfg_opt_logic_y3um67y.sv(330): going to vhdl side to elaborate module altera_debug_master_endpoint File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_y3um67y.sv Line: 330
Info (19337): VHDL info at altera_debug_master_endpoint.vhd(120): executing entity "altera_debug_master_endpoint(addr_width=11,has_rdv=0,slave_map="{typeName altera_xcvr_native_a10 address 0x0 span 8192 hpath {} assignments {dataRate 8000000000 protMode basic_enh pmaMode basic txPowerMode mid_power device_revision 20nm1}}")(1,175)(1,1)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_debug_master_endpoint.vhd Line: 120
Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=35,receive_width=45,num_clocks=1,settings="{fabric mapped dir agent addr_width 11 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_a10 address 0x0 span 8192 hpath {} assignments {dataRate 8000000000 protMode basic_enh pmaMode basic txPowerMode mid_power device_revision 20nm1}}} prefer_host { } clock_rate_clk 0 psig b6c1a030}")(1,298)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
Info (16822): Verilog HDL info at alt_xcvr_native_rcfg_opt_logic_y3um67y.sv(330): back to verilog to continue elaboration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_y3um67y.sv Line: 330
Warning (16788): Net "rcfg_emb_strm_chan_sel[0]" does not have a driver at alt_xcvr_native_rcfg_opt_logic_y3um67y.sv(166) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_y3um67y.sv Line: 166
Warning (16788): Net "g_jtag.jtag_readdatavalid" does not have a driver at alt_xcvr_native_rcfg_opt_logic_y3um67y.sv(293) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/pcie_xcvr_test/pcie_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_y3um67y.sv Line: 293
Info (16821): Verilog HDL info at altera_transceiver_reset_endpoint.v(39): going to vhdl side to elaborate module altera_a10_xcvr_reset_endpoint File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_transceiver_reset_endpoint.v Line: 39
Info (19337): VHDL info at altera_a10_xcvr_reset_endpoint.vhd(120): executing entity "altera_a10_xcvr_reset_endpoint" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_a10_xcvr_reset_endpoint.vhd Line: 120
Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=2,receive_width=1,settings="{fabric a10_xcvr dir agent use_clock 0 needs_clock 0 psig 6b6bab39}")(1,67)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
Info (16822): Verilog HDL info at altera_transceiver_reset_endpoint.v(39): back to verilog to continue elaboration File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_transceiver_reset_endpoint.v Line: 39
Info (16821): Verilog HDL info at alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv(330): going to vhdl side to elaborate module altera_debug_master_endpoint File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv Line: 330
Info (19337): VHDL info at altera_debug_master_endpoint.vhd(120): executing entity "altera_debug_master_endpoint(addr_width=11,has_rdv=0,slave_map="{typeName altera_xcvr_native_a10 address 0x0 span 8192 hpath {} assignments {dataRate 10312500000 protMode basic_enh pmaMode basic txPowerMode mid_power device_revision 20nm1}}")(1,176)(1,1)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_debug_master_endpoint.vhd Line: 120
Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=35,receive_width=45,num_clocks=1,settings="{fabric mapped dir agent addr_width 11 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_a10 address 0x0 span 8192 hpath {} assignments {dataRate 10312500000 protMode basic_enh pmaMode basic txPowerMode mid_power device_revision 20nm1}}} prefer_host { } clock_rate_clk 0 psig b6c1a030}")(1,299)" with architecture "rtl" File: c:/intelfpga_pro/18.0/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
Info (16822): Verilog HDL info at alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv(330): back to verilog to continue elaboration File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv Line: 330
Warning (16788): Net "rcfg_emb_strm_chan_sel[0]" does not have a driver at alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv(166) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv Line: 166
Warning (16788): Net "g_jtag.jtag_readdatavalid" does not have a driver at alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv(293) File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/sfp_xcvr_test/sfp_xcvr_test_xcvr_native_c10_0/altera_xcvr_native_a10_180/synth/alt_xcvr_native_rcfg_opt_logic_4z3yzzy.sv Line: 293
Error (16045): Instance "q_sys_inst0|pcie_xcvr_test_1c_0|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_0|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_0|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_0|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/synth/pcie_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_0"
Error (16045): Instance "q_sys_inst0|pcie_xcvr_test_1c_1|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_1|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_1|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_1|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/synth/pcie_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1c_1"
Error (16045): Instance "q_sys_inst0|pcie_xcvr_test_1d_2|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_2|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_2|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_2|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/synth/pcie_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_2"
Error (16045): Instance "q_sys_inst0|pcie_xcvr_test_1d_3|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_3|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_3|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_3|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/pcie_xcvr_test/synth/pcie_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|pcie_xcvr_test_1d_3"
Error (16045): Instance "q_sys_inst0|sfp_xcvr_test_1d_0|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_0|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_0|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_0|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/synth/sfp_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_0"
Error (16045): Instance "q_sys_inst0|sfp_xcvr_test_1d_1|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" instantiates undefined entity "xcvr_test_system_data_pattern_generator_0_altera_avalon_data_pattern_generator_180_xz7276a" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_1|xcvr_test_system_0|data_pattern_generator_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0/synth/xcvr_test_system_data_pattern_generator_0.v Line: 35
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_1|xcvr_test_system_0|data_pattern_generator_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/xcvr_test_system/synth/xcvr_test_system.v Line: 10
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_1|xcvr_test_system_0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/sfp_xcvr_test/synth/sfp_xcvr_test.v Line: 51
Error (16185): Can't elaborate user hierarchy "q_sys_inst0|sfp_xcvr_test_1d_1"
Error (16185): Can't elaborate user hierarchy "q_sys_inst0" File: D:/cerebriq/altera development kits/qts_pcie_sfp/qts_pcie_sfp/qts_pcie_sfp.v Line: 18
Error (16186): Can't elaborate top-level user hierarchy
Error: Flow failed: 
Error: Quartus Prime Synthesis was unsuccessful. 35 errors, 71 warnings
	Error: Peak virtual memory: 5937 megabytes
	Error: Processing ended: Sun Oct 28 08:58:48 2018
	Error: Elapsed time: 00:00:20
	Error: Total CPU time (on all processors): 00:00:24