List of designs using Altera External Memory IP

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List of designs using Altera External Memory IP

Designs by FPGA Family

Stratix V

• Design Example: Stratix V Six Dual Rank DDR3 SRAM UniPHY 667MHz x72 ; SV UniPHY, DDR3 667MHz, Quartus 13.0
• Design Example: Stratix V QDR II+ SRAM UniPHY 550 MHz x18 using external PLL ; SV UniPHY, QDR II+ 550MHz, Quartus 12.0
• Design Example : Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate; SV UniPHY, DDR3 667MHz, Quartus 12.0 
• Design Example : Multiple Memory interface Using Uniphy Quartus II v11.1 ; SV UniPHY,DDR3 450MHz, Quartus 11.1
• Design Example : Multiple Memory interface Using Uniphy ; SV UniPHY,DDR3 450MHz, Quartus 11.0

Stratix IV

• Design Example - Stratix IV QDR II+ SRAM UniPHY 400MHz x18: SIV UniPHY, QDR II+ SRAM 400MHz x18, SIV GX FPGA development kit, Quartus 11.0
• Design Example - Stratix IV DDR3 SDRAM UniPHY 400MHz x8 using Qsys: SIV UniPHY, DDR3 400MHz x8, SIV FPGA development kit, Quartus 11.0
• Design Example - Stratix IV DDR3 SDRAM UniPHY 533MHz x64: SIV UniPHY, DDR3 533MHz x64, SIV GX FPGA development kit, Quartus 11.1
• Design Example - Stratix IV RLDRAM II UniPHY 533MHz x36: SIV UniPHY, RLDRAM II 533MHz x36, SIV E FPFA development kit, Quartus II 11.1
• Design Example - Basic DDR3 UniPHY bring up : SIV, UniPHY, DDR3 533MHz x16, SIV FPGA development kit, Quartus 10.1
• Reference Design : PCI Express to External Memory - Stratix IV ALTMEMPHY DDR3 PCIe Gen1x8 : SIV FPGA development kit, Quartus 9.0
• Design Example - SIV ALTMEMPHY DDR3 400MHz - 3 Shared Controllers : Quartus 8.1
• Design Example - SIV ALTMEMPHY DDR3 400MHz - Four Controllers : Quartus 8.0SP1
• Design Example - SIV ALTMEMPHY DDR3 533MHz x64 - SIVGX Development Kit : Quartus 9.0SP0.03
• Design Example - SIV ALTMEMPHY RLDRAMII 400MHz x18 - Eight Controllers : Quartus 8.1

Stratix III

• Design Example - SIII ALTMEMPHY RLDRAMII 300MHz x72 : Quartus 8.1
• Design Example - SIII ALTMEMPHY RLDRAMII 300MHz x18- SIO : Quartus 8.1
• Design Example - Stratix III DDR2 SDRAM ALTMEMPHY x72 UDIMM 400MHz: Quartus 9.0
• Design Example - Stratix III DDR2 SDRAM SODIMM ALTMEMPHY 333MHz x64: Quartus II v8.0SP1
• Design Example - Stratix III DDR3 SDRAM ALTMEMPHY 533MHz x72: Quartus II v9.1
• Design Example - Stratix III QDRII SRAM ALTMEMPHY 400MHz x18: Quartus II v8.0
• Design Example - Stratix III DDR2 SDRAM UniPHY 400MHz x72 Quartus II v11.1
• Design Example - Stratix III QDRII SRAM UniPHY 333MHz: Quartus 11.1
• Design Example - Stratix III RLDRAM II UniPHY 400MHz: Quartus 11.1 

Stratix / Stratix II

• Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 333MHz x72: Quartus II 7.2
• Design Example - Stratix II ALTMEMPHY DDR2 267MHz - Three Controllers: Quartus 9.0
• Design Example - Stratix II GX DDR2 SDRAM LEGACY PHY 267MHz x72: Quartus II 7.2
• Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 200MHz x8 - Native Interface: Quartus 9.1

Arria 10

• Design Example - Arria 10 Hard Memory Controller DDR3 933MHz Quarter Rate x72 Dual Rank UDIMM  Quartus II v14.1
• Design Example - Arria 10 DDR3 SDRAM 1067MHz Quarter Rate x40 with EMIF Debug Toolkit Quartus II v15.0

Arria V

• Reference Design - Arria V Hard Memory Controller Bonding Interface: Quartus II v12.0
• Design Example – Arria V Hard Memory Controller DDR3 SDRAM UniPHY 533MHz x32  Quartus II v12.0sp1

Arria II

• Design Example - Arria II GX DDR2 SDRAM ALTMEMPHY 267MHz x64: Quartus II v9.1
• Design Example - Arria II GX DDR3 SDRAM ALTMEMPHY 300MHz x16: Quartus II v9.1

Arria I

Cyclone V

• Reference Design - Cyclone V Hard Memory Controller with Avalon-MM data width expanded for User ECC: Quartus II v13.1

Cyclone IV

Cyclone III

• Design Example - CIII ALTMEMPHY DDR2 150MHz x8 - SOPC Builder : Quartus 9.1
• Design Example - Cyclone III DDR2 SDRAM ALTMEMPHY 167MHz x32: Quartus 7.2

Cyclone / Cyclone II

Max 10

• Max10 DDR3 UniPHY Half Rate 300MHz x24:Quartus 15.0
• Max10 LPDDR2 UniPHY Half Rate 200MHz x16 : Quartus 15.1.2 

DDR3

• Design Example - Arria 10 Hard Memory Controller DDR3 933MHz Quarter Rate x72 Dual Rank UDIMM  Quartus II v14.1
• Design Example - Arria 10 DDR3 SDRAM 1067MHz Quarter Rate x40 with EMIF Debug Toolkit Quartus II v15.0
• Max10 DDR3 UniPHY Half Rate 300MHz x24:Quartus 15.0
• Reference Design - Cyclone V Hard Memory Controller with Avalon-MM data width expanded for User ECC: CV UniPHY, DDR3 400MHz, Quartus II v13.1
• Design Example: Stratix V Six Dual Rank DDR3 SRAM UniPHY 667MHz x72 ; SV UniPHY, DDR3 667MHz, Quartus 13.0
• Design Example – Arria V Hard Memory Controller DDR3 SDRAM UniPHY 533MHz x32 Quartus II v12.0sp1
• Reference Design - Arria V Hard Memory Controller Bonding Interface: Quartus II v12.0
• Design Example - Stratix IV DDR3 SDRAM UniPHY 400MHz x8 using Qsys : SIV UniPHY, DDR3 400MHz x8, SIV FPGA development kit, Quartus 11.0
• Design Example - Stratix IV DDR3 SDRAM UniPHY 533MHz x64: SIV UniPHY, DDR3 533MHz x64, SIV GX FPGA development kit, Quartus 11.1
• Design Example - Basic DDR3 UniPHY bring up : SIV UniPHY, DDR3 533MHz x16, SIV FPGA development kit, Quartus 10.1
• Reference Design : PCI Express to External Memory - Stratix IV ALTMEMPHY DDR3 PCIe Gen1x8 : SIV FPGA development kit, Quartus 9.0
• Design Example - SIV ALTMEMPHY DDR3 400MHz - 3 Shared Controllers : Quartus 8.1
• Design Example - SIV ALTMEMPHY DDR3 400MHz - Four Controllers : Quartus 8.0SP1
• Design Example - SIV ALTMEMPHY DDR3 533MHz x64 - SIVGX Development Kit : Quartus 9.0SP0.03
• Design Example - Stratix III DDR3 SDRAM ALTMEMPHY 533MHz x72: Quartus II v9.1
• Design Example - Arria II GX DDR3 SDRAM ALTMEMPHY 300MHz x16: Quartus II v9.1

DDR2

• Design Example - Arria II GX DDR2 SDRAM ALTMEMPHY 267MHz x64: Quartus II v9.1
• Design Example - CIII ALTMEMPHY DDR2 150MHz x8 - SOPC Builder : Quartus 9.1
• Design Example - Stratix III DDR2 SDRAM ALTMEMPHY x72 UDIMM 400MHz: Quartus 9.0
• Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 333MHz x72: Quartus 7.2
• Design Example - Cyclone III DDR2 SDRAM ALTMEMPHY 167MHz x32: Quartus 7.2
• Design Example - Stratix II ALTMEMPHY DDR2 267MHz - Three Controllers: Quartus 9.0
• Design Example - Stratix II GX DDR2 SDRAM LEGACY PHY 267MHz x72: Quartus II 7.2
• Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 200MHz x8 - Native Interface: Quartus 9.1
• Design Example - Stratix III DDR2 SDRAM SODIMM ALTMEMPHY 333MHz x64: Quartus II v8.0SP1
• Design Example - Stratix III DDR2 SDRAM UniPHY 300MHz x72 Quartus II v11.1

DDR

LPDDR2

• Max10 LPDDR2 UniPHY Half Rate 200MHz x16 : Quartus 15.1.2 

QDR / QDRII / QDRII+

• Design Example: Stratix V QDR II+ SRAM UniPHY 550 MHz x18 using external PLL ; Quartus 12.0
• Design Example - Stratix IV QDR II+ SRAM UniPHY 400MHz x18: SIV UniPHY, QDR II+ SRAM 400MHz x18, SIV GX FPGA development kit, Quartus 11.0
• Design Example - Stratix III QDRII SRAM UniPHY 400MHz: Quartus 11.1
• Design Example - Stratix III QDRII SRAM ALTMEMPHY 400MHz x18: Quartus II v8.0

RLDRAM / RLDRAMII

• Design Example - SIV ALTMEMPHY RLDRAMII 400MHz x18 - Eight Controllers : Quartus 8.1
• Design Example - SIII ALTMEMPHY RLDRAMII 300MHz x72 : Quartus 8.1
• Design Example - SIII ALTMEMPHY RLDRAMII 300MHz x18- SIO : Quartus 8.1
• Design Example - Stratix III RLDRAM II UniPHY 400MHz: Quartus 10.0
• Design Example - Stratix IV RLDRAM II UniPHY 533MHz x36: SIV UniPHY, RLDRAM II 533MHz x36, SIV E FPFA development kit, Quartus II 11.0 

See Also

•   Guidelines - Multiple Memory interface Using ALTMEMPHY
•   Guideline and check list to troubleshoot in calibration failure

External Links

1. Altera's External Memory Interface Solutions Center
2. Altera's External Memory Interface Handbook

Key Words

UniPHY, HPCII, HPCI, HPC, High Performance Controller, AltMemPHY, DDR3, DDR2, DDR, QDR, QDRII, QDRII+, RLDRAM, RLDRAMII, Reference Design, Design Example, External Memory, EMI, EMIF, Qsys, HMC

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