High-Speed Transceiver Demo Designs - Intel® Stratix® 10 TX Series

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High-Speed Transceiver Demo Designs - Intel® Stratix® 10 TX Series

High-Speed Transceiver Demo Designs - Intel® Stratix® 10 TX Series

 

Index

Multi-Prbs Generators and Checkers

Intel® Stratix® 10 LVDS Test Designs

1. LVDS PHY

Intel® Stratix® 10 TX

1. Script with useful procedures for use in system console for Stratix 10 TX (E-Tile)

2. Library of C-functions for E-tile transceivers using AVMM Interface

3. Hard PRBS Test Designs

4. Soft PRBS + Dynamic Reconfiguration Test Designs

5. Soft PRBS + RSFEC + Dynamic Reconfiguration Test Designs

6. Superlite IV (using Native PHY) (with FEC)

7. Superlite IV (using EHIP Core or EHIP Lane) (with FEC)

8. Superlite II V4 (with/without FEC)

9. 100GbE

10. 25GbE

 

Multi-Prbs Generators and Checkers

 

  • New (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths : 32-bit, 64-bit, 128-bit and 256-bit. Includes testbench as well. 

 

Intel® Stratix® 10 LVDS Test Designs

 

1. LVDS PHY

 

  • (26/03/2020) Fully parameterizable Stratix 10 LVDS Phy Module to transport a wide databus across multiple LVDS Lanes with DPA (inc. 4 channel Loopback Demo design for the S10GX SI board)

Stratix 10 TX

 

1. Script with useful procedures for use in the system console for Stratix 10 TX (E-Tile)

       

2. Library of C-functions for E-tile transceivers using AVMM Interface

 

  • Functions for configuring PMA settings, adaptation, etc. (These are the same functions as used in the 5x24 Soft PRBS Demo Design) :
  • Updated (26/11/2020) 

 

3. Hard PRBS Test Designs

 

  • (28/11/2019) Stratix 10 TX SI Board (Production Rev B1) : 60 channel PAM4/NRZ Design at 57.8 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically) + PMA configuration supports + I2C etc.

 

  • (31/10/2019) Stratix 10 TX SI Board (S1) : 60 channel PAM4/NRZ Design at 57.8 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically) + PMA configuration supports + I2C etc.

 

  • (23/08/2019) Stratix 10 TX SI Board (Production Rev B1) : 120 channel Dual Mode (NRZ/PAM4) at 28.3 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically) + PMA configuration supports + I2C etc.

 

  • Updated (23/08/2019) Stratix 10 TX SI Board (S1) : 120 channel Dual Mode (NRZ/PAM4) at 28.3 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically) + PMA configuration supports + I2C etc. (Requires updated regulator settings to run all channels > 25 Gbps)

 

4. Soft PRBS + Dynamic Reconfiguration Test Designs

 

  • Updated (12/01/2021) Stratix 10 TX SI Board (Production Rev B1): 5x 24 channel NRZ/PAM4 28.3 Gbps soft PRBS test design (allows to reconfigure from NRZ to PAM4 dynamically) + LPM + PMA configuration supports + I2C etc.

 

  • (28/04/2020) Stratix 10 TX SI Board (Production Rev B1): 5x 12 channel PAM4/NRZ 57.8 Gbps soft PRBS test design (allows to reconfigure from PAM4 to NRZ dynamically) + LPM + PMA configuration supports + I2C etc.

 

  • Updated (28/05/2020) Stratix 10 TX SI Board (Production Rev B1): 2x 4 channel NRZ/PAM4 28.3 Gbps soft PRBS test design connected to QSFP-DD 2x1 that can be dynamically reconfigured to :
    • another profile (design has 2 profiles)
    • another referenceclock (switch between refclk[0] and refclk[1]
    • change dynamically the frequency of refclk[0] or refclk[1]
    • including Adaptation Soft IP in each PHY + LPM + PMA configuration supports + I2C etc.
    • prbs_2x4ch_ETILE_30Gbps_dual_mode_qsfp_2x1_ODI_adapt_sip_DR.zip (20.1 B177)

 

 

  • Updated (19/11/2019) Stratix 10 TX SI Board (S1): 2x 8 channel PAM4/NRZ 58 Gbps soft PRBS test design with Adaptation Soft IP in each PHY connected to QSFP-DD 1x1 and QSFP-DD 2x1 (allows to reconfigure from PAM4 to NRZ dynamically) + LPM + PMA configuration supports + I2C etc.

 

  • Updated (27/02/2019) Stratix 10 TX SI Board (S1): 2 channel PAM4/NRZ 58 Gbps soft PRBS test design connected to SMA_A and SMA_B (allows to reconfigure datarate as well as encoding (PAM4/NRZ) dynamically on tranmit and receive seperately)

 

5. Soft PRBS with RSFEC + Dynamic Reconfiguration Test Designs

  • Recently Updated (15/02/2022) Stratix 10 TX SI Board (Production Rev B1) : 2x 4 channel NRZ 28.3 Gbps soft PRBS with RSFEC in FRACTURED mode test design that can by dynamically reconfigured to :
    • NRZ/PAM4 RSFEC Fractured (528,514) (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate)              
    • NRZ/PAM4 RSFEC Fractured (544,514) (line rate is 26.5625 Gbps from 156.25 Mhz clock (x170) or any reconfigurable rate)   
    • PAM4 KPFEC Aggregate (544,514) with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate) 
    • NRZ PMA direct mode with 4 physical lanes (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate) 
    • PAM4 PMA direct mode with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate) 
    • Reconfigure individual lane 1-3 from RSFEC to PMA direct (line rate is (tx_clk_divider (configurable)  x refclk frequency) and PMA direct to RSFEC fractured.
    • when all lanes are in PMA direct NRZ mode : reconfigure lane 0-3 to any reconfigurable datarate (line rate is (tx_clk_divider (configurable)  x refclk frequency)
    • Connected to QSFP-DD 2x1 + Adaptation Soft IP in each PHY, + LPM + PMA configuration supports + I2C etc.
    • s10-tx-siboard-2x4ch-etile-qsfp-2x1-adapt-sip-rsfec-fract-to-kpfec-aggr-and-pma-direct.zip (21.4 B67)

 

  • New (07/05/2021) Stratix 10 TX SI Board (Production Rev B1) : 2x 4 channel NRZ 28.3 Gbps soft PRBS with RSFEC in FRACTURED mode with External AIB/EMIB clocking test design that can by dynamically reconfigured to :
    • NRZ/PAM4 RSFEC Fractured (528,514) (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165))               
    • NRZ/PAM4 RSFEC Fractured (544,514) (line rate is 26.5625 Gbps from 156.25 Mhz clock (x170))
    • PAM4 KPFEC Aggregate (544,514) with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2))
    • NRZ PMA direct mode with 4 physical lanes (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165))  
    • PAM4 PMA direct mode with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2))  
    • Connected to QSFP-DD 2x1 + Adaptation Soft IP in each PHY, + LPM + PMA configuration supports + I2C etc.
    • This design allows independent reset in RSFEC fractured mode on all 4 channels.
    •  prbs-2x4ch-ETILE-qsfp-2x1-adapt-sip-rsfec-fract-to-kpfec-aggr-and-pma-direct_ext-emib.zip (20.4 B72)

 

  • (26/02/2020) Stratix 10 TX SI Board (Production Rev B1) : 2x 4 channel NRZ/PAM4 28.3 Gbps soft PRBS with RSFEC in FRACTURED mode test design with Adaptation Soft IP in each PHY connected to QSFP-DD 2x1 (allows to reconfigure from NRZ to PAM dynamically) + LPM + PMA configuration supports + I2C etc. (Note the design above is a superset and is more recent than this one).

 

  • (15/01/2020) Stratix 10 TX SI Board (Production Rev B1) : 2x 4 channel NRZ/PAM4 28.3 Gbps soft PRBS with RSFEC in AGGREGATE mode test design with Adaptation Soft IP in each PHY connected to QSFP-DD 2x1 (allows to reconfigure from NRZ to PAM dynamically) + LPM + PMA configuration supports + I2C etc.

 

  • Updated (14/06/2021) Stratix 10 TX SI Board (Production Rev B1) : 2x 8 channel PAM4 56 Gbps soft PRBS with KPFEC test design with Adaptation Soft IP in each Link connected to 2 QSFP-DD 1x1 + LPM + PMA configuration supports + I2C etc.

 

 

6. Superlite IV (using Native PHY) (with FEC)

PAM4

 

 

  •  (17/04/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (+ I2C & Fan Control + tested with 400G Optics) (Native PHY + KPFEC)

 

 

 

NRZ

 

7. Superlite IV (using EHIP Core or EHIP Lane) (with FEC)

PAM4

 

  • (07/01/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (EHIP Core + KPFEC)

 

NRZ

 

8. Superlite II V4 (with/without FEC)

 

 

9. 100GbE

  • New (26/02/2021) Stratix 10 TX SI Board (Prod) : 100GbE Dynamic Reconfiguration design (out-of-the-box) (using Tcl). Design can be dynamically reconfigured to 
  • CAUI-4 (4 x 25.78125 Gbps NRZ with RSFEC(528,514) aggregate) 
  • CAUI-2 (2 x 53.125 Gbps PAM4 with KPFEC(544,514) aggregate)
  • GAUI-4 (4 x 26.5625 Gbps NRZ with KPFEC(544,514) aggregate)
  • CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) 

 

  • Updated  (16/02/2021) Stratix 10 TX SI Board (Prod) : 100GbE Dynamic Reconfiguration design (using Nios). Design can be dynamically reconfigured to 
  • CAUI-4 (4 x 25.78125 Gbps NRZ with RSFEC(528,514) aggregate) 
  • CAUI-2 (2 x 53.125 Gbps PAM4 with KPFEC(544,514) aggregate)
  • GAUI-4 (4 x 26.5625 Gbps NRZ with KPFEC(544,514) aggregate)
  • CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) 

 

 

 

10. 25GbE

Version history
Last update:
‎08-01-2023 02:11 PM
Updated by:

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