Conditional assignments with generics

Altera_Forum · ‎07-25-2008

Is it possible in VHDL to assign a signal conditionally based on the value of a generics without creating additional unwanted logic?

I think the following code created logic to evaluate the condition.

signal_a <= signal_b when (GENERIC_A > GENERIC_B)

else signal_c;

Altera_Forum · ‎07-25-2008

What you wrote should work OK. You shouldn't get a 2:1 mux for a conditional assignment with a condition that's a compile-time constant. You could use a conditional generate, but VHDL doesn't have an if/else version of a generate, e.g.


GEN_TRUE: if (GENERIC_A > GENERIC_B) generate
begin
   signal_a <= signal_b;    
end generate GEN_TRUE;
GEN_FALSE: if not(GENERIC_A > GENERIC_B) generate
begin
   signal_a <= signal_c;
end generate GEN_FALSE;

So I'd probably stick with what you've got.

Altera_Forum · ‎07-25-2008

Thanks for your reply. I tried the generate and the original way I had it and they both produce the same result. When the conditionals are in there, my design doesn't pass the timing requirement on those signals, but if I take the conditionals out it works just fine. Maybe it is a Quartus bug.

Altera_Forum · ‎07-25-2008

If one version fails timing, did you analyze the difference between the critical paths in the passing and failing versions. It could be that you're on the cusp of meeting timing and small netlist changes or random placement variations are enough to push you over or under your timing constraint(s).

Altera_Forum · ‎07-26-2008

Generally, Quartus isn't generating any unwanted logic. It's removing unneeded signals and registers unless explicitely told to keep it by synthesis attributes. The only disadvantage of using generics in conditional expresions is that you get some warnings regarding constant expressions. But it's the only plausible method to achieve conditional compilation inside a process, so the warnings should be accepted. You can expect a lot of similar meaningless warnings with parameterizable designs.

Cause place and route is performed after minimizing logic expressions, I can't imagine why the synthesis should end up with different timing.