What memory to choose SRAM or SDRAM?

[Altera_Forum]

Hi All, 

Need a help!!! What memory to choose SRAM or SDRAM?  I have standard analog NTCS video signal that digitalized to a digital signal 8bits and then entered to Cyclone III (EP3C25F324). I have 3 big tasks that my project must be able to do: 1) To rotate the picture 90 degrees in real time (may be 1 frame delay) and send it out to the DAC to convert it beck to NTCS analog signal. 2) To save some frames on external memory in order to make any DSP processing.  3) To save bmp (1 frame 640x480) of the rotated signal on the SD card. The board managed by silicon labs microprocessor, which controls all the board components and FPGA. I know that I must use external parallel memory, in order to store and rotate the video signal.  But I don’t understand what memory more suitable for my case and easier for interfacing: SRAM, , SDRAM, DDRAM, 2DDRAM… As reference I saw Altera development kits, but I still don’t know what memory I should choose.  I am electronics engineer and about a 1.5 year experience with FPGA.   Thanks Alex

[Altera_Forum]

SRAM has less density than DRAM (this means you can store less data) but it's faster in general. DRAM is more difficult to interface as it stores data using capacitors that need to be refreshed from time to time or else they lose the stored data. If you want to achieve both high density and high data rate, you should try some DDR SDRAM module. Micron is a good vendor as it provides them in non-DIMM packages along with their datasheets so you wont have to look for chips used in PC's . If you want to use SRAM, Cypress is a good solution as it combines high density and high data rate (DDR and QDR SRAM). As it gets more complicated so does the vhdl code (interface) you have to write. Of course there is a lot of IP out there either free or not, better or worse, that does the job.

[Altera_Forum]

SRAM is : 

1 - Low Latency - happy 2 - Low Density - sad 3 - Easy to interface to - happy 4 - Expensive - sad  DRAM is: 1 - High Latency - sad 2 - High Density - happy 3 - Hard to interface to - sad . However, using Altera's memory controller makes this much easier - happy 4 - Cheap - happy  Jake

[Altera_Forum]

I have two questions regarding DRAM/SDRAM and hopefully somebody in this forum can help me. I tried them with Micron and another manufacturer but they would not go into detail since they claimed confidentiality. 

Question# 1. If for some reason I can store the row address and if there is a row hit and I would be able to retrieve the row right away. Can I cut down on the number of tRCD clock cycles (typically 2 clocks) or better yet can I completely eliminate it. What I meant was can I skip the Ras cycle and retrieve row addresses from the register, decoded them at the same time column addresses are selected. The second question is if I am at the same row addresses but need access to different bank. Can I just decode the bank at the same time I decode column address since the new bank is valid during the entire cycle (both Ras & Cas). It looks like in the datasheet that it still takes tRCD cycles. My argument is you do not have to reload the row address since it is the same and bank and column addresses can be decoded at the same cycle and therefore you can shave one or get rid of tRCD cycles completely. Thank you very much for any response. Regards, SML

[Altera_Forum]

use a NIOS core , u can use the SDRAM/DDR SDRAM as a sram