How to make the output of PLLs in differrent FPGA devices synchronous with each oth

[Altera_Forum]

PLLs in differrent devices have the same settings and the same clock source(as attached plot). I need the PLL output of clk1 and clk2 to be synchronous with each other. How to do it? Could you help me

[Altera_Forum]

Hi, 

 Fore me it seems like  Try to connect the PLLs with a dedicated line (see the board layout manual) for Ex: CoreClk (10MHz) : in std_logic;  oClk <= CoreClk;  Take an extra port oClk : out std_logic; (in Device 1) and iClk : in std_logic ; (in Device 2)  and also try to adjust the different phases which can be statistically set in MegaCore Wizard.

[Altera_Forum]

I doubt you will be able to achieve that goal. 

At 250 MHz, the period is only 4 ns. The worst case difference is only +-2 ns  How tight are you looking to get them?

[Altera_Forum]

Basically, a clock that is a multiple of inclock has a defined and reproducable phase by design. Deviations are expectable only from delay skew, but I can't see how to reduce them further by any means beyond the initially achieved synchronity.

[Altera_Forum]

I would like to ask the question, where there is the reason to do so? 

The design method of synching two devices from the outside , lead me to the conclusion, that there ist the intention to transport data from one device to the other in one clock.  This hardly will work due to jitter. One should better perform synching on the data speed level or use frame synching methods within the system.

[Altera_Forum]

Jitter can't be expected to be basically lower in a source synchronous design than with an external clock, I think. But delay variations (skew) may actually reduce the sampling window down to or even below zero for a 250 MHz clock. 

 A defined clock phase relation can be desirable also for a source synchronous design.

[Altera_Forum]

"AND" the 'locked' signals of both the PLLs and write logic to use clocks with this global "locked" signal.