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I am wondering if it is possible to create Modelsim (DE 10.0a) covergroups with PSL(VHDL).
I couldn't find any documentation, and I'm starting to have doubts about its feasibility. I know how to create cover points, but is there a keyword that I missed or a kind of structure type that would do the job? Or is SystemVerilog (and Questasim) mandatory for that? Thank you. DamienLink Copied
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A covergroup is a SystemVerilog construct. PSL only has individual cover directives.
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Thank you for your confirmation Dave.
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