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Microtronix non-Avalon multi-port memory controller

Altera_Forum
Honored Contributor II
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All,  

 

Here are the datasheets of Microtronix' IPs: 

- High Performance Avalon Multi-Port SDRAM Memory Controller IP core, and 

- High Performance Streaming Multi-Port SDRAM Memory Controller IP core (NEW!). 

 

If you have any questions, please contact Microtronix (http://www.microtronix.com). 

 

Best Regards, 

 

--jmv
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Altera_Forum
Honored Contributor II
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I was wondering if anyone here has tried the Microtronix non-avalon multi-port controller? I am having a strange issue with it.

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Altera_Forum
Honored Contributor II
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I suggest that you contact Microtronix to discuss your strange issue. 

 

--jmv
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Altera_Forum
Honored Contributor II
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Hi, 

what is meant by "Intelligent SDRAM burst caching minimizes wait-states"?:confused:  

Are the request (RD or WR) resorted, so that there are a minimum of bank precharges and the controller tries to write (or read) the longest possible burst length supported by the memory? 

 

Regards 

 

Christian
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Altera_Forum
Honored Contributor II
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Hi, 

we have tried the Microtronix non-avalon multi-port controller. And in our evaluation phase we had no problems with the IP-Core. We were also able to reach the promised speed in a test implementation. 

We didn't run a design in hardware. We verified the functionality in simulation to find out if it meets our requirements.
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Altera_Forum
Honored Contributor II
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Hello Christian, 

 

You're right. The FIFOs are concatenating individual port accesses into one long access to the SDRAM memory. This minimizes the total CAS latency compared to single transfers.  

 

Best Regards, 

 

Marco
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Altera_Forum
Honored Contributor II
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Hi Marco, 

 

thanx for the reply. :)  

 

Christian
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