Quartus II 7.1 - SOPC Builder New Component

[Altera_Forum]

Does anyone have experience with making new components for SOPC Builder in Quartus II 7.1? 

 I've had good luck with generating components for SOPC Builder when they are simple modules that span a single file.  However, I've noticed that that component wizard does not allow for designs that span multiple files. Now if I copy each module into a single file, everything works fine. But that's not conducive to design reuse. Has anyone found a solution to this?  Also, I've noticed that sometimes the component wizard has trouble determining the size of the address bus when using generics. Has anyone heard of this problem?

[Altera_Forum]

I guess you can just add the top-level file, which has all the avalon ports. All the other files will be added for synthesis in the synthesis process. 

Component wizard is a "port-parsing" program. No need to provide all the sub-level files.

[Altera_Forum]

I have also noticed this. The problem Im finding is that the analyzer will not find any of my package files. I tried addign the library 'work' to the project which contained the package, but this still did not work. Anyone figure this out?

[Altera_Forum]

For the analyzer to find your files, you need to add their location as a user library. 

 Another alternative (which I have not tried but I think will work): After you create the component using the Wizard, edit the generated class.ptf file to include the other files. There should be a section called DEFAULT_GENERATOR which declares the other files. Try to look at some example components and you will figure out what to do there.  Once you do this, when you generate your SOPC system, all the files will get copied to your project directory and thus you will not need to add them to your user libraries.  Good Luck,  Ziad

[Altera_Forum]

It seems that in 7.1, no original design files will be copied to the project directory. All the generated design files are instantiations of the original design files(file wrappers), except for the top level sopc design file.  

When doing synthesis and analysis, we should add the original design files manulally in the Files page of the Settings menu.  This is different from previous versions of Quartus. I think this is an improvment. Let the Synthesizer do the file locating job. The Component editor only checks the interface signals but not those lower level files.

[Altera_Forum]

--- Quote Start ---  Does anyone have experience with making new components for SOPC Builder in Quartus II 7.1?  I've had good luck with generating components for SOPC Builder when they are simple modules that span a single file.  However, I've noticed that that component wizard does not allow for designs that span multiple files. Now if I copy each module into a single file, everything works fine. But that's not conducive to design reuse. Has anyone found a solution to this?  --- Quote End ---    I have a similar problem where I'd like to create a single file VHDL component that uses a package for defining some common types/constants used in this file. This used to work fine in pre 7.1 SOPC for the analysis of files in the component editor wizard because you could add multiple files. However, i can only specify a single file for this now and hence when it analyses the component file that uses my package it fails with errors.  I have also come across the problem with multiple files and the change in bahaviour. I have to explicitly add each file in Quartus or add a project library path in order to compile.    --- Quote Start ---  Also, I've noticed that sometimes the component wizard has trouble determining the size of the address bus when using generics. Has anyone heard of this problem?  --- Quote End ---    I also have a problem with components that define variable data and address widths with generics using the new 7.1 component method - *_hw.tcl. This worked fine using the legacy .ptf method pre 7.1. For example, a generic defining the address width for a simple test component with a master port and adding this component with an address width setting of 32 to try and access internal memory I get the error :  Error: PP_AvalonDummyMaster_3.dummy_m: "onchip_mem_1.s1" (0x10010000..0x1001003f) outside range (0x0..0x1)  The onchip memory for this test is 64 bytes located at 0x10010000.  Can anybody help?

[Altera_Forum]

I also faced the problem of using packages when introducing a new component to the SOPC-Builder. A service request to Altera came up with the following solution: Use the old version 7.0 or wait for the new version 7.2 coming in two month, because the Nios II 7.1 has some problems!!! :eek: :eek:  

A simpler workaround is to copy the entire package code into the component's top level file. Not nice, but it works!

[Altera_Forum]

I have had exactly the same problem. I made a modified DMA component (with variable increment, and wrap to make a circular buffer), which works fine in 7.0, but in 7.1 I get the outside range (0x0..0x1) error. I have no idea what some of the interface properties do (such as 'addressGroup'), and I can find no reference to a complete list of interface properties and what they mean. The Quartus manual, section 6, 'Building a Component Interface with TCL commands' offers very little information, and is missing interface definitions that appear in the generated _hw.tcl files. Can anyone help by pointing at a document that lists the interface properties. And also how to overcome this address range problem. Thanks!

[Altera_Forum]

Yeah I'd also be interested in finding some more information on building components from the tcl file.  

The Gui definitely adds more parameters to the _hw.tcl file than are documented. And at the moment it seems that manually editing the _hw.tcl file is the only way to create a component that uses the streaming interface.

[Altera_Forum]

Hi 

I had the same error and I fixed the problem: When the sopc refreshes the components list it need to have also the vhd file (not only the tcl) in order to know the ports width. so: 1. make sure the top level vhdl is in the directory of the project, or if you prefer, in other directory that you added to the project (global or local) 2. in the tcl, second row: "set_module" have to be the exact name of the vhdl entity.  enjoy.

[Altera_Forum]

--- Quote Start ---  I have had exactly the same problem. I made a modified DMA component (with variable increment, and wrap to make a circular buffer), which works fine in 7.0, but in 7.1 I get the outside range (0x0..0x1) error. I have no idea what some of the interface properties do (such as 'addressGroup'), and I can find no reference to a complete list of interface properties and what they mean. The Quartus manual, section 6, 'Building a Component Interface with TCL commands' offers very little information, and is missing interface definitions that appear in the generated _hw.tcl files. Can anyone help by pointing at a document that lists the interface properties. And also how to overcome this address range problem. Thanks!  --- Quote End ---    Hi BartSchroder,  It seems that in 7.1 component editor it may have incorrectly inserted a tcl parameter that limits the address span size.  Look for the following addressSpan parameter: set_interface_property "<slave port>" "addressSpan" "<some_span_value>"  where <slave port> is the name of the Avalon Slave port.  There seems to be two ways to fix this issue 1) comment out the parameter with a# at the begining of the line (or just delete it) 2) correctly calculate the correct address span value which should be the total number of addressable bytes (2^address_bits * word_size_in_bytes).  It seems that the component editor when it inserted the addressSpan parameter it sometimes did not use the correct address span value. But if you remove that parameter, the SOPC Builder will correctly calculate the address span of your component.  It seems if there is a tcl parameter that is not documented in ch 6 'building a component interface with tcl commands' (http://www.altera.com/literature/hb/qts/qts_qii54022.pdf) (http://www.altera.com/literature/hb/qts/qts_qii54022.pdf) it may not be a required parameter and can usually be commented out of the file with little issue.   What I do is use the component editor to build the initial tcl file and then modify the tcl file directly when I need to make changes. I also found commenting out the tcl parameter not documented in the ch6 seems to make my component less prone to issues like the addressspan issue above. I seen to have the most sucess following this way of creating a component in 7.1.  Regards, -ATJ