File not simulating with ModelSim-Altera

[Altera_Forum]

Hello guys, I have the following two projects. The first one Simulates perfectly in modelsim-altera, but the second one does not show output. I want to know where is the problem in the second one??? By the way, both of them Simulate with quartus ii simulator, but I want to use ModelSim-Altera Simulator because it is better. Of course, some might think that I must have done something wrong during the Simulation with ModelSim, but then I ask, how come the first design runs without problem?? I just give value to the clock and get the output perfectly. I really appreciate your help.  

 1st design    --------------- Frequency division by 2 -----------------------------------`   library IEEE;  use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity freq_div_2 is port(  clk : in STD_LOGIC;  out_clk2 : out STD_LOGIC ); end freq_div_2; architecture freq_div_2_arc of freq_div_2 is begin divider : process (clk) is variable m : integer range 0 to 3 := 0;  variable n : std_logic := '0';  begin if (falling_edge (clk)) then  m := m + 1; if (m = 1) then m := 0; n := not n; end if ; end if; out_clk2 <= n;  end process divider; end freq_div_2_arc;  ---------------------------------------------------------------------------------------------  2nd design  ---------------------- Frequency division by 2 -------------------  LIBRARY ieee;  USE ieee.std_logic_1164.all;  -----------------------------------------  ENTITY freq_div2 IS  PORT ( clk : IN STD_LOGIC;  out2 : BUFFER STD_LOGIC);  END freq_div2;  -----------------------------------------  ARCHITECTURE example OF freq_div2 IS  BEGIN  PROCESS (clk)  VARIABLE count2 : INTEGER RANGE 0 TO 7;  BEGIN  IF (clk'EVENT AND clk='0') THEN  count2 := count2 + 1;  IF (count2 = 1) THEN  out2 <= NOT out2;  count2 := 0;  END IF;  END IF;  END PROCESS;  END example;  -----------------------------------------

[Altera_Forum]

Hi,  

 I think there is something with output port type declared as a buffer. I never use ports declared as a BUFFER. Use signals and assign them to output ports. I would change your code to something like this:   ---------------------- Frequency division by 2 ------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ----------------------------------------- ENTITY freq_div2 IS PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; out2 : OUT STD_LOGIC); END freq_div2; ----------------------------------------- ARCHITECTURE example OF freq_div2 IS signal clk_div : std_logic; BEGIN PROCESS (clk, reset_n) BEGIN IF reset_n='0' THEN clk_div<='0'; IF (clk'EVENT AND clk='0') THEN clk_div<= NOT clk_div; END IF; END PROCESS; out2<=clk_div; END example;  By the way why is yor process trigered from falling clock edge?

[Altera_Forum]

First of all, thank you very much for your code. I checked it and it works perfectly. As for why I use the falling edge of the clock, it's because it makes the comparison between the clock and the output easier. Now, do you think I could extend your code to divide by (4,6,8,......)??? Thank you for your help really.

[Altera_Forum]

Do not mix in your design registers clocked from falling and rising edges except you are implementing DDR registers. If you are using single edge use only risig edge. 

   --- Quote Start ---  Now, do you think I could extend your code to divide by (4,6,8,......)??? Thank you for your help really.  --- Quote End ---    Yes you can. Add counter which is incremented every clock cycle. Toggle clk_div signal when counter reaches certain amount (depends on divide by value), reset counter.

[Altera_Forum]

Thank you very much, I took your advice and now the design works perfectly. But, I have one last question if you don't mind. I have thought about the program and now I want to divide the clock by (2,3,4,5,6,7....) rather than (2,4,6,8,10,12....) what can I do now?? The counter is integer, so when (the counter = 2 => divides by 4), when  

(counter=3 => divides by 6 and so on. But, suppose I want to divide by 3. I can't say when counter = 1.5 because it's integer. Thank you for your help.

[Altera_Forum]

--- Quote Start ---  Thank you very much, I took your advice and now the design works perfectly. But, I have one last question if you don't mind. I have thought about the program and now I want to divide the clock by (2,3,4,5,6,7....) rather than (2,4,6,8,10,12....) what can I do now?? The counter is integer, so when (the counter = 2 => divides by 4), when  (counter=3 => divides by 6 and so on. But, suppose I want to divide by 3. I can't say when counter = 1.5 because it's integer. Thank you for your help.  --- Quote End ---    Hi I never tried to implement this kind of clock divider. Why do you need such clock divider? I think in this case you will need to implement two counters. One trigered from rising edge second - from falling. Then you have to check when total count value of both counters rech your div value eg. 3. As I said before never tried this myself, just my thougts.