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This is part of the Verilog SoC 'light' tutorial. The simple circuit works correctly on the board. But while running a functional simulation, this error is given.
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 16:37:06 on Jan 10,2017# vlog -work work light.vwf.vt # -- Compiling module light_vlg_sample_tst# -- Compiling module light_vlg_check_tst# -- Compiling module light_vlg_vec_tst# ** Error: light.vwf.vt(171): 'i1' already declared in this scope. # End time: 16:37:06 on Jan 10,2017, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: c:/altera/15.0/modelsim_ase/win32aloem/vlog failed. # Executing ONERROR command at macro ./light.do line 4 Error. ------ I have not missed any tutorial steps and I am certain the Verilog is correct. Here it is just for reference. module light(i1, i2, f); input i1, i2; output f; assign f = (i1 & ~i2)|(~i1 & i2); endmodule This error is occurring in a generated file which I am not at all familiar with. Any help would be much appreciated. Thanks, DevinLink Copied
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Devin -
Have you looked at the light.vwf.vt file to see if you can find the problem? ModelSim told you exactly what it gagged on.
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