How to implement PCI Express into my project.

[Altera_Forum]

Hello, 

 I have created the PCIe project according to example mentioned in PCI Express Compiler User Guide(2nd chapter). After compilation, pin assignment and programming the StratixIIGX my PC can recognize the device[1].  But i cant find any reference how to implement that PCIe project into my own. For example, my project has the output pins that carry the data that i need to transfer to PC trough PCIe. How can i connect them to the previously created project mentioned above[1].  I tried to make one project that is attached here. But it doest work. PC doesn't see the Device.  Any suggestions are highly appreciated.  Best regards, Igor.

[Altera_Forum]

Hi, 

 I'm having the same problem but it is with PCI Compiler. I create the PCI registers and bars using the PCI Compiler. Quartus generates a time limited .sof file. I send the configuration file to PCI kit, and when I reset the computer (BIOS has to identify the PCI device before O.S boot) nothing happens. The computer just doesn't turn on.  Have you got any idea about what's happening?  tks

[Altera_Forum]

hi, i have the same problem.  

someone can answer this problem?

[Altera_Forum]

RFX, 

 I contact altera's support. But it didn't help. I send to them another especific question about our problem. I'm waiting for the answer. I'll send you new informations as soon as altera answers me.  I've opened reference design files to compare reference's pci code (that code generated by pci compiler) with mine code. It's exactly the same thing (it changes just some BARs memory size). Device ID, Vendor ID and the others fields of PCI registers are equal to reference's code.  Do you know if , when BIOS start to recognize PCI devices plugged on the computer, is there a transaction that localside of PCI megafuntion has to deal with it?  I'm saying this because I just implement in my project control functions to deal with read and write PCI transactions. Maybe we have to make something else.

[Altera_Forum]

Hello, I don't think that localside of PCI megafunction need to deal with the PC BIOS starting up. Because I know somebody has deal it with pcie-to-pci bridge interface correctly. But there is some difference between them. Now I'm not sure neither. 

 By the way, I'm dealing the pcie megafunction. However, I think it is the same as pci megafunction. It also need I deal with read and write transactions in my project control functions. So I sometimes has the same idea as you. Maybe we have to make someting else with the BIOS. If that, I think the megacore is so bad.:(

[Altera_Forum]

I look at books about PCI and I found the configuration transaction of PCI device. Generally BIOS start this proceeding: There's 2 kinds of configuration transaction: type 0 and type 1. 

PCI device has to respond to this transaction to BIOS recognizes it. The functionality of PCIe has the same procedure.  I'll start to look in the reference and examples files to see if there's a clue. If you look at a read or write transaction example files of PCIe Compiler (.vwf files) you1re going to see that before read/write command there's a configuration write/read transaction.

[Altera_Forum]

Hi, I found that one of my card can be found when pc start up. So I think that ip megacore completes the configuration transaction automatically. But now, I don't kown why the other two card can't run correctly. Maybe the jointing is not good. I'll send you new informations as soon as I find something else.

[Altera_Forum]

Dude, 

 I got some vital sign from my dev board. Still BIOS does not recognize the PCI board. I think you can help me. Please tell me the steps that you've made when you'd created your PCIe design.  I'm doing these steps: 1) create a new project 2) run the megawizard to create a instance of PCI Megafunction 3) run the tcl script to add teh pci timing constraints 4) set the pinout location for my design 5) compile the project 6) see it again not working :o(  tks

[Altera_Forum]

Hi, First you can determine if you have the Link training state machine in L0 state and the LED on the board indicating x1 or x4 or x8 link established. (depending if you have an adapter connected to the board to plug it into a x4 or a x1 slot). The link training bits are bits 324..320 of the test_out port and you can see them in signaltap. 

 If you are not linking properly, double check that you are meeting timing in your project and if not, add constraints. You may want to monitor other test_out port signals to see what else is happening.

[Altera_Forum]

Hi guys, 

 I could make the board to be recognizes by PC. SignalTap and test_out signals can help to identify the problem. Another thing is that there are some timing violations in the project. If i start sending/reading the data, after a few cycles the board fails and then cannot be recognized by PC till the next reset.  It is important to enter all the parameters in megacore manager properly.   Does anyone of you managed to make the board working stable while reading/writing the data?  Best wishes for a pleasant day!  Igor.

[Altera_Forum]

Hi guys, 

 We were also trying to modify Chaining DMA Example design in a way to incorporate our own custom Endpoint design into it. Ultimately, the design was supposed to stream data to and from PC through PCIe.  Although the project can be compiled and the board is detected by PC correctly, so far we were unable to feed data from FPGA to PC and verify it's reception on PC's side.  In this relation, if you could share any bits of information/design files/projects/tips regarding your positive experiments with PCI Express Compiler it would be much appreciated.  Thanks in advance, Maxim.

[Altera_Forum]

In the pex_example_top you can find altpcierd_master entity which is responsible for DMA. There is a memory implemented there - altsyncram - You can send/receive data through datain and dataout signals in the altpcierd_master entity. 

 Please send your updates.  Igga

[Altera_Forum]

Hi Igga, 

 Thanks for your update.    --- Quote Start ---  In the pex_example_top you can find altpcierd_master entity which is responsible for DMA.  --- Quote End ---   - <variation name>_example_top.v for Simple DMA doesn't appear to have such entity. Nevertheless, I suppose under -   --- Quote Start ---  datain and dataout signals  --- Quote End ---   - you were referring to rx_inN and tx_outN signals - correct me if I'm wrong.  In addition, what tools do you use to verify sent and received data?  I believe the entity you referring to (altpcierd_master) is actually located in altpcierd_example_app.v  Kind regards, Maxim.

[Altera_Forum]

Hi friend, 

 It seems that we are using different examples. Im using the example created by megacore wizard, like it was described in the PCIE Compiler User Guide. The second thing is that im using Quartus v6.0 with PCIE compiler 2.1.0.   In that example you can use access either DMA or target memory writing or reading from altsyncram RAM memory. To verify the data im using the application program supplied with the development kit (Application GUI).  I can attach my project shortly if necessary.  Igor.

[Altera_Forum]

Hi Igor, 

 Yes, we do use different designs - I'm using Quartus v 7.2 and PCIe Compiler v 7.2. Thus the designs are different.  If it does not bother you much, can you still attach your project so we can have a look? It might give us some clues.  Thanks in advance, Maxim.

[Altera_Forum]

Hi buddy, 

 Sorry for the late reply. My license for the Quartus has expired and i was waiting for the new one. Im attaching my simple project. You can see the one single value was assigned to datain signal. It is the simplest way to feed the data from FPGA to PC(use dataout to transmit the data from PC to FPGA). You can use Application GUI to check it.  Take care, Igor

[Altera_Forum]

Hi, 

 Another option is to look at the constraints of a working design such as: http://www.altera.com/support/refdesigns/ip/interface/ref-pciexpress-hp.html This example contains a .qar file for the Stratix II GX Altera board and a basic Windows-XP software application which works with the provided .sof file.  Good luck.  Lili Bebcnofne