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JTAG Cable Issues (and Solutions)

Altera_Forum
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I’ve seen a number of boards with JTAG issues. Some fail outright, some issues are intermittent, etc. Since JTAG is being used in so many ways, it tends to manifest itself in a number of situations, such as configuration issues, SignalTap II issues, Nios II programming issues, etc.  

 

Anyway, we talked to the main developer at www.universalscan.com about it and he brought up some interesting points. (Quick Plug: The users I know who have the Universal Scan tools have all been extremely happy with the tools, support, etc., so look at the GUI and Downloads section to see if it’s something that might help you…) 

 

- He sees JTAG issues all the time, and with all vendors. This is usually not a cable issue per se, but more of a result that the JTAG connections are done at the last minute and usually where ever there is space on the board. Users generally route the 4 JTAG nets alongside each other and think, since it’s a slow test interface, its not susceptible to noise. 

 

- TCK is a clock. Remember to treat it like one in board layout 

 

- A JTAG cable is a long antennae that goes through many connections(cabling, buffers, star topologies on the board, etc.) 

 

- On most, (probably all, but I haven’t checked), Altera devices, the TDI and TMS signals are clocked in on the rising edge of Tck, while the Tdo is clocked out on the falling edge. The TDI and TMS tend not to be a problem since they transition far away from the Tck transitions, but Tdo transitions occur at roughly the same time. 

 

This is important if you look at his App note 003. Go to www.universalscan.com, click on FAQ -> Download Cable Questions -> Click on Appp Note 003. This shows how easy it is to couple the Tdo transitions onto the Tck clock. 

 

- Fast buffers are not always best. They tend to create very fast edge rates, which are more susceptible to signal integrity issues. He actually recommended using an older, slower buffer for JTAG chains. (Our issue was actually a double pulse on the Tck line going into the on-board buffer, so this wasn’t the problem, but the buffer saw two clocks and made two distinct edges out of them. Naturally, the best solution is to remove the double-clocking in the first place.) 

 

- Although the glitch in the app note is large, they can be much smaller and still cause a problem, and more importantly, they can be easy to miss with a scope. In our case, we have scope shots of the Tck line at all points, and could not identify a glitch, but adding a 220 ohm resister cleaned it up and got it working again. 

 

Anyway, you can see the recommendations at the bottom of the app note. It helped in our case, and I realized most JTAG layouts I’ve seen are susceptible to noise issues, since the TCK and TDO run alongside each other for long distances without any consideration for signal integrity. 

 

Hope that helps.
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Altera_Forum
Honored Contributor II
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I am the beginnner of using the altera cyclone 11 .... when i connect my usb  

blaster cable to the pc, it is not detected . Plz help me in solving this problem. Thanks in advance.
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