Writing data to output file VHDL

[Altera_Forum]

Hi all, 

 I'm working with a DE2 Altera board Quartus II 6.1 and am trying to take data that I receive from the board, and send it to an output file, a text file.   There will be a lot of data so I don't want to use the output LEDs or LCD. I found this simple code online, but it will not compile on my machine b/c I get the following error:  Error (10481): VHDL Use Clause error at printing.vhd(5): design library "IEEE" does not contain primary unit "std_logic_textio"  Does anyone know how I can perform a simple output to file????  library STD; -- you don't need STD, it is automatic library IEEE; -- but may need other libraries use IEEE.std_logic_1164.all; -- basic logic types use STD.textio.all; -- basic I/O use IEEE.std_logic_textio.all; -- I/O for logic types  ENTITY printing IS  port (  abc :in std_logic  ); END printing;  architecture test of printing is -- where declarations are placed  subtype word_32 is std_logic_vector(31 downto 0); -- simple name  signal four_32 : word_32 := x"00000004"; -- just four in hex  signal counter : integer := 1; -- initialized counter begin -- where parallel code is placed  my_print : process is -- a process is parallel  variable my_line : line; -- type 'line' comes from textio  begin  write(my_line, string'("Hello World")); -- formatting  writeline(output, my_line); -- write to "output"  write(my_line, string'("four_32 = ")); -- formatting   hwrite(my_line, four_32); -- format type std_logic_vector as hex  write(my_line, string'(" counter= "));  write(my_line, counter); -- format 'counter' as integer  write(my_line, string'(" at time "));  write(my_line, now); -- format time  writeline(output, my_line); -- write to display  wait;  end process my_print; end architecture test;   -- compile/analyze this file  Thanks  Paul

[Altera_Forum]

You are mentioning a DE2 Altera board. Are you trying to do this on hardware or is it a test bench simulation? 

 What simulator are you using? I know that the ieee.std_logic_textio package is included i ModelSim. I don't know about NCsim and simulation inside Quartus. You might need to install/map additional libraries and packages.  For hardware, the textio packages are simply not synthezisable. What kind of interface is it from the board to where you are trying to write a file?

[Altera_Forum]

I think what you're trying to do is analyse how data differs from one run to another. 

 If you use Signal Tap Logic Analyser, you have an option of extracting the result in a neat text format.  I found this information in this thread: http://www.alteraforum.com/forum/showthread.php?t=764&highlight=text+file