modelsim 6.1g AE and port mapping

Altera_Forum · ‎08-14-2007

Hi everybody,


machine_com : entity communication
PORT MAP (	clk => sysclk,
			E_com(7 downto 0) => diag(7 downto 0),
			S_com(19 downto 9) => V_inter(19 downto 9)
			);

The port S_com is 20 downto 9 and I really want to ignore S_com(20).

This code fails to compile on modelsim ae 6.1g but is synthetisable in quartus 7.1 :confused: .

Maybe a small bug to fix.:)

Altera_Forum · ‎08-15-2007

The "entity" is the typo? This is weird. Perhaps you can try compile with -93 switch (e.g. vcom -93 ...)?

Altera_Forum · ‎08-28-2007

Nope.

What do you mean by "the entity is typo" ?