Parallel in, serial out

[Altera_Forum]

Hi.. 

 Can any body know, how can i make parallel input to serial output in quarts2 ?  In my application, i have 6 input (6 pin in FPGA) and i want output(1 pin).How to do it in quartus2 (or in VHDL)??    for example..  input1:1 input2:0 input3:1 then output:101001. input4:0 input5:0 input6:1  Thanking you.

[Altera_Forum]

You could try using the lpm_shiftreg megafunction. If you're using a schematic design file, double click on a blank area and select it from libraries/megafunctions/storage. Select bus width of 6, serial shift out, parallel data in. Shift direction depends on how you connect up your inputs. You'll need to think about where you get parallel load and clock signals from. 

 That's one way, at least. Hope it helps.

[Altera_Forum]

If the TX and RX are synchronized you can do a little counter feeding a multiplexer like below... If they aren't you need a UART or something similar to recover the data alignment.  

 ---  module test (rst,clk,in,out);  input clk, rst; input [5:0] in; output out;  reg [2:0] state; always @(posedge clk) begin  if (rst) state <= 0;   else begin  if (state == 5) state <= 0; // wrap around early  else state <= state + 1'b1;  end end  wire [7:0] data = {2'b00,in}; // make the data a power of 2, only 6 are used assign out = data[state];  endmodule

[Altera_Forum]

--- Quote Start ---  You could try using the lpm_shiftreg megafunction. If you're using a schematic design file, double click on a blank area and select it from libraries/megafunctions/storage. Select bus width of 6, serial shift out, parallel data in. Shift direction depends on how you connect up your inputs. You'll need to think about where you get parallel load and clock signals from.  That's one way, at least. Hope it helps.  --- Quote End ---    Thanks for you help..  Ok.. clock is not a problem, but if i put load = 1 and load = 0 then what is the changes on output ??

[Altera_Forum]

It's a synchronous load, so if it's high when the clock rises, your parallel data will be latched in. Depending on which direction you are shifting, either bit 0 or bit 5 (your inputs 1 and 6) will appear on the serial output and the subsequent clocks will shift out the rest. I'm not sure without checking, but there might be a delay between the load and your first data bit appearing at the output. Also, I'm not sure where the serial output will settle after your last data bit is shifted out. If this matters, add the 'serial in' port to your megafunction and tie it high or low. You could frame your data in UART fashion by adding some extra bits either side of your data bits and tying them high and low as required. 

 The best thing to do is read the Quartus built-in help for this function. Look under 'megafunctions' in the index. Then play with it. To me that's half the fun.