I use SDR SDRAM Controller to control SDRAM. The port looks like follows:
--inputs:
signal az_addr : IN STD_LOGIC_VECTOR (25 downto 0);
signal az_be_n : IN STD_LOGIC_VECTOR (7 downto 0);
signal az_cs : IN STD_LOGIC;
signal az_data : IN STD_LOGIC_VECTOR (63 downto 0);
signal az_rd_n : IN STD_LOGIC;
signal az_wr_n : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
--outputs:
signal za_data : OUT STD_LOGIC_VECTOR(63 downto 0);
signal za_valid : OUT STD_LOGIC;
signal za_waitrequest : OUT STD_LOGIC;
signal zs_addr : OUT STD_LOGIC_VECTOR(12 downto 0);
signal zs_ba : OUT STD_LOGIC;
signal zs_cas_n : OUT STD_LOGIC;
signal zs_cke : OUT STD_LOGIC;
signal zs_cs_n : OUT STD_LOGIC_VECTOR(3 downto 0);
signal zs_dq : INOUT STD_LOGIC_VECTOR(63 downto 0);
signal zs_dqm : OUT STD_LOGIC_VECTOR(7 downto 0);
signal zs_ras_n : OUT STD_LOGIC;
signal zs_we_n : OUT STD_LOGIC;
My ueser logic reads and writes data via SDR SDRAM Controller from and to SDRAM.
I define follow signals for read operation.
az_addr <= (other 0);
az_rd_n <= '0'; --read enable
az_wr_n <='1'; --write disable
clk and reset_n signal are also assigned
and az_cs <= '1';
az_be_n<="11111111" --data mask disable
write operation
az_data<="11111...1" -- 64 bits
az_rd_n <= '1'; --write enable
az_wr_n <='0'; --read disable
clk and reset_n signal are also assigned
and az_cs <= '1';
az_be_n<="11111111" --data mask disable
But I can not get back the data. I don't know if in my assignment somewhere is wrong. I have tried for many times.
