Error in simulation verification

[Altera_Forum]

Hi all. 

 I am new to quartus II software. I am trying to functionally simulate a ckt (it is a simple 2 input 'and' gate). I have put on the 'check output' option as I want to compare the results to expected output.   But I am getting the following error:   Error: Simulation results from C:/altera/71/quartus/db/and.sim.cvwf (0 ps to 40.0 ns) do not match expected results from vector source file C:/altera/71/quartus/and.vwf  Error: Logic level 0 does not match expected logic level 1 for node "Result" at time 30.0 ns  I am running the simulation for 40 ns. The 'and.vwf' is my vector source file in which the value for 'result' (output of 'and' gate in my ckt) is 1 at 30 ns. It is 1 in the simulation output waveform too(that I check in the simulation report).   Actually my bigger goal is to know if the following is possible in quartus II:  Suppose I have an 'and' gate with 'a' & 'b' as inputs and 'result' as output. - Is there a way to input my test values for 'a' & 'b' from a file, rather than having to set the waveform for them using the waveform editor tool. Because if I have lots of values to set for 'a' or 'b', doing that manually by way shown in the help tutorial (i.e by selecting the waveform period and setting it to 1 or 0) can be very tedious.  - Second, I want to check if the output values are correct over the entire testing period. One way is to compare manually all the values, but again this cud be really tedious. Is there a way that the simulator can do this comparison and let me know the answer sth like 'yes' or 'no' the match occurs. I believe sth like this is what the 'simulation verification' settings allow. but am still not able to figure out clearly.  any help wud be really appreciated. thanks !  regards, anu

[Altera_Forum]

The Quartus native simulator can use a couple of types of text files for inputs, but they might not be much easier than a waveform file to create manually. You might be better off using a test bench and a third-party simulator or ModelSim-Altera Edition. The test bench can both specify the input stimulus and check the results. (The Quartus native simulator can't use a test bench.) 

 If you want to continue with the Quartus native simulator, there might be an easier way to create the "lots of values to set for 'a' or 'b'". To test all possible combinations of a and b, you can group them and give them a count sequence. Select a and b, right click, and select "Grouping --> Group". Select the resulting group, right click, and select "Value --> Count Value".  If a and b are individual signals (not buses), another method without a group is to overwrite a and b individually with clock values of different periods that together produce all possible combinations of a and b values. If they are buses, overwrite a and b separately with count values, but use different count periods for a and b so that a and b together produce all combinations.