undefined clock in synthesis

Altera_Forum · ‎08-18-2007

Hi,

so i created a ram block in Quartus with megafunction wizzard. It is a 2-port MK4, i set it to auto, but it came out to be MK4. So it has one read, one write port, wren, clk, and addresses for read and write. I needed two of those for single-cycle: data memory and instruction memory, but i made only one component although in test bench i have 2 DUTs. Compiles fine with no warnings/errors. Source runs fine with these warnings:

# ** Warning: Warning: READ_DURING_WRITE_MODE_MIXED_PORTS is assumed as OLD_DATA

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut3/altsyncram_component

# ** Warning: Warning: Port B will take the address_reg_b parameter as

reference clock source for Port B, which is CLOCK0

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut3/altsyncram_component

# ** Warning: Warning: READ_DURING_WRITE_MODE_MIXED_PORTS is assumed as OLD_DATA

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut2/altsyncram_component

# ** Warning: Warning: Port B will take the address_reg_b parameter as

reference clock source for Port B, which is CLOCK0

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut2/altsyncram_component

so i dug altera documentation but it was not very informative.

When i run SYNTHESIZED version of design in modelsim, i get a bunch of undefines, including the CLOCK! i am not sure what is going on. Should i have created two separate components of ram even though they are the same? instead of having 1 component and 2 instances of it?

Thanking you in advance.

Altera_Forum · ‎08-20-2007

The read during write output is referring to the build options for an output register. That is not related to a memory megafunction failing. I assume you want output registers, and that is not the first thing to worry about.

The first step I would take a look at is your simulation stimulus signals. Since you are debugging in simulation, (good job) you are likely building your own reference clock. Take a look in simulation at the clock in the context (scope) of the test bench. Make sure it is working at the top level before it gets to the megafunction. Once that is working, follow it down through the heirarchy until it goes X.

Altera_Forum · ‎08-21-2007

well, what actually happened is that one component was not bound and somehow modelsim did not catch that in source, but once i fixed that and resynthesized, clock was ok. Also another thing is that i synthesize ram since it's FPGA internal, every time i update memory init. file i have to resythesize it.