signal tap question

[Altera_Forum]

This is what my circuit's RTL looks like: rtl (http://img250.imageshack.us/img250/9601/img001cx1.jpg) 

It is a ring oscillator, similar to this (http://www.alteraforum.com/forum/showthread.php?t=709) post.  I'm programming an Altera Cyclone III Board. Trying to view the outputs using SignalTap [similar to viewing it on a scope, right?]. I'm unable to view pin dout, because when I try to add node dout to Signal Tap - I get an error -- pre-synthesis nodes cannot be added to a signaltap ii instance that is incrementally compiled.   Alright, so dout is a pre-synthesis node. Don't think I can change that. So let me try to disable incremental compilation. Assignments > Settings > Compilation Process Settings. But the incremental compilation menu is greyed - maybe because I'm using the free version of Quartus?   I can view the ring oscillator's output by viewing LC_1 (see RTL image). But I would like to see what goes on at dout too. Any ideas?  ***  I'm a month-old FPGA person. Please be kind if my question sounds silly.

[Altera_Forum]

Look in the SignalTap chapter of the Quartus handbook. It talks about using post-fitting nodes for incremental SignalTap (as well as some other things that I think are still required in version 7.1).

[Altera_Forum]

If you want to use pre-synthesis nodes, you can turn off incremental compile for the SignalTap instance itself by using the "Incremental Compile" checkbox in the instance manager. This can be hidden sometimes. Make sure the window is shown by going to View -> Instance Manager. Then uncheck the Incremental Compile checkbox. 

 The other option, is to use the post-fit filter to add your nodes, as Brad mentioned.