more questions about signal tap

[Altera_Forum]

I'm creating a simple ring oscillator, to observe the frequency variations of a free running oscillator, among other things.  

 Inspired by the forum gurus, I went through the 68 page signal tap manual. I still have a few questions though ....  1. In signal tap, while specifying sample depth - I have an option of spec a max of 128k samples. So the device buffers are sampled 128k times. This question maybe naive but -- 128k samples / ___? is it 128k samples/sec?   2. I read that -- "SignalTap II Logic Analyzer continuously captures data while it is running. To capture and store specific signal data, you set up triggers that tell the logic analyzer under what conditions to stop capturing data." So at what speed does the Logic Analyzer capture data? At the speed of the acquisition clock -- "The logic analyzer samples data on every rising edge of the acquisition clock."   In my design, I have no acquisition clock, so Signal Tap adds one - auto_step_externalclk_0 -- to which I do not assign any signal. My data tab still reads random signals ~ which seem to be, but may not necessarily be oscillating. Where are these coming from? .... Random SRAM values? See the RTL and Signal tap screenshot for my design -- here (http://img66.imageshack.us/img66/8792/helpdt4.gif).  3. How is the sample depth different from the frequency of the acquisition clock? ... Is it that the data is sampled at every rising edge of the acq clock and stored in allocated buffers. The sample depth frequency indicates the frequency at which this stored data is sampled from the buffers?   4. When I click on run analysis (not auto run analysis), the analysis runs and stops. What determines the time for which the analysis runs?   5. Incremental Compiling - is disabled in my Quartus Web Edition. Signal Tap adds a lot of extra stuff in the chip planner. Does it add anything at all to the design with the paid version? That's a good incentive to push 'them' to get me one.   6. I'm basically concerned with getting a 'clean' output for my RO. Looks like it would be sampled twice, once from the signal, then from the buffer. And I'm not sure if the Signal Tap functionality is further distorting it in some way. What's the cleanest way to get my outputs?   Any help will be MUCH appreciated. I do not personally know anybody else using Quartus, and these answers seem difficult to figure out by myself..... Thank you!

[Altera_Forum]

1) The sample rate is determined by the clock you select. Whatever frequency that clock runs at will be your sample rate. It has nothing to dowith the depth of samples. 

 2) This goes back to# 1. The speed of capture is the speed of the sample clock. The fact that signal tap continuously samples tells you that the sample storage is always active, and the trigger simply stops the sample and uploads to your computer a snapshot of the sample buffer controlled by your trigger.  3) The acquisiton clock controls the sample rate going into the buffers. Comming out of the buffers to your computer for display is JTAG on a different and unrelated clock domain.  If your sample clock is not too fast for signal tap, you will be fine getting a clean sample.

[Altera_Forum]

Whoa, thanks!! I think I see what you're saying. SignalTap samples the signals at the acquisition clock frequency and stores it in the device buffers. I can specify how many such samples [sample depth] I want to see after the trigger happens.  

 To get an accurate representation of the signal, my acq clock should be atleast 2x the frequency of the signal [Nyquist frequency]. To be safe, maybe 10x, if Signal Tap can take it. I read the maximum clock freq is 200MHz.   If my acquisition clock does not go high at all, Signal Tap samples nothing, so 128k samples [sample depth] of nothing get stored in the SRAM when trigger [power up trigger] happens. so my output is garbage -- just SRAM init states [ah, I ran the analysis on that!].   The time for which the analysis runs, is the time taken for the buffers to get full after the trigger happens.   I'm just re-iterating my understanding. Correct me, please, if I am wrong.  Thanks a million :) :)

[Altera_Forum]

Yes, now it sounds like you are on the right track. I would have said one thing a little different. If the acquisition clock never toggles, the sample memory does not capture anything. It is true you would be looking at just SRAM initial data if you stopped the capture at that point.

[Altera_Forum]

Thanks Randall. Another thing I read was that I should use a non-gated clock as acquisition clock for best results with Signal Tap. How can I add a non-gated clock to my VHDL code....? 

 Thanks!

[Altera_Forum]

I would assume you already have a clock. Signal tap simply samples the signals you tell it to sample into on-chip memory using the rising edge of the clock you tell it to use. If you have a signal tap working, you would have had to give it a clock. The non-gated guidance tells you a little more about how to get signal tap to work right. Any signal can be made a "clock" simply by using it to drive the clock input of a register. What is normally thought of as a clock is one of these clock signals that is also driven by a clock buffer, so you can think of it as having almost negligable skew across the part. Then it can be thought of as a typical clock domain. More specific than that, signal tap wants you to use either an input pin (assumed to be driven by a clean clock source), or an output from an on-chip PLL. A register output would also qualify as non-gated, but then you would need to ensure it gets on a global net. Signal tap does not want you to derive a signal with combinatorial logic and call that a clock. That would messes up the timing.

[Altera_Forum]

Just a heads up - the ring is going to need to be pretty big to get down to 100MHz for Signal Tap sampling. Cyclone II reports this 25 cell path at 91MHz. This is a worst case guarantee, actual silicon speed will be faster. 

 ---  module test (clk,out); input clk; output out; reg out;  wire [24:0] stall /* synthesis keep */; assign stall[24:0] = {stall[23:0],out};  always @(posedge clk) begin  out <= stall[24]; end endmodule

[Altera_Forum]

--- Quote Start ---  Signal tap does not want you to derive a signal with combinatorial logic and call that a clock. That would messes up the timing.  --- Quote End ---    Thanks, Randall for this pointer. I found out I could use CLOCK_50 ~ 50MHz for the acquisition clock... I owe my ST knowledge to you!   ---  Gsynth, in your code --- I broke the chain and unclocked it to see the propagation delay through the chain. you are right, apart from the first LCELL which has a considerable propagation delay (don't know why), the remaining transitions happen really fast....   I tried it on chip with Signal Tap [I know how it works now, yaay] and the transitions seem to happen almost simultaneously. I wonder where my delay is going to come from, at this rate. :(