Quartus Problems

[Altera_Forum]

I have been using Quartus II for quite a while maybe starting with 5.0 web edition. I have a problem that I always keep running into and maybe someone can help me out. The problem involves me getting erratic results. I have used cyclone II and cyclone devices on the trex and de2 boards from terasic. I don't believe that the chips or dev boards are at fault, I believe it is how I use the software. I have also used the software on a 5v MAX 7000 part and it was rock solid. I have never paid much attention to timing constraints and such. I just make my modules with Verilog and connect them together in a block diagram file adding pins and then compile. Most of the time things go fine, but sometimes I will add just one more element to the block diagram and everything will stop working - like no signals in or out of the chip! After unraveling what changed, I will be back in business. Can anyone please explain what might be going on here. Is it timing problems? Where would I find information on this kind of problem? Thanks in advance!

[Altera_Forum]

You didn't provide much about your design or method to work with looking for your problem. You already suspect you need to do timing constraints. That is generally true. The book HDL chip design by Douglas Smith is very practical and gives a great overview of how to do design, such as what matters and how do it. Do you use synchronous design techniques? Do you use a global asynchronous (i.e. power up) reset?  

To ensure your part is alive: 1) check powers are in spec. DMM at least, scope better 2) check the part always configures, esp. with LED's 3) check the clock source with a scope to ensure proper levels and integrity 4) check the internal clocks working, with signal tap, PLL locked, etc. 5) ensure synchronous and meets timing Once you are generally working you can troubleshoot an individual function.

[Altera_Forum]

I am using a Logicport 32 channel PC based logic analyzer hooked up to divider outputs from the FPGA. The fpga always programs properly. When I have the "erratic behavior" the outputs of the dividers as seen on the logic analyzer just appear dead - no division, no output at all. This must have to do with my own ignorance of using Quartus because if others had this problem I think this forum would be one big hate Quartus party! I just don't understand why when I seem to have something working properly just adding another piece of unrelated logic can stop the whole system in its tracks. I am not trained in digital logic but have studied Verilog on my own and built my share of 4000 and 7400 series of logic circuits. By the way, this is not just a problem with my own logic circuits. Some of the Altera DE2 examples from Terasic have similar problems. Just changing one simple thing can affect unrelated modules and give unexpected results. Come on, tell me if I am being stupid or admit that this has happened to some of you also! Thanks again.

[Altera_Forum]

There is no short answer until you have verified the basics. After ensuring your part is running with the basic assumptions met, then yes you need to make your design synchronous and apply timing constraints.