Help: What's the difference between functional simulation and timing one

[Altera_Forum]

I have a project and the functions are OK when i run functional simulation,but when i tried timing one ,it didn't work as i designed ,it seems as if it didn't work. In some other projects the problem also exists. 

I don't know what's wrong with it, and should i do something with the time assignments? what can we get from timing simulation? Could you help me? Thank you very much.

[Altera_Forum]

When timing simulation, you may need a Vector Waveform File(in New, Other Files menu). In that file, you can indicate the I/O pin(s) and after simulation you can see the waveform from these I/O pin(s). 

 My English is poor, i wonder whether i understand your problem correctly.:)

[Altera_Forum]

Functional Simulation simply tests the logic "functional" operation of the circuit. There is no consideration for delay through the internal logic or the routing dealy paths associated with where the placer and the router interconnect things. 

It simply allows you to see that what you think you are coding provides the results you are intending.  With Timing Simulation, the delay asociated with the logic elements and the interconnect routing are taken into consideration (based on the speed grade of the chip selected).  Delays may result in signals not meeting setup time, etc. which could explain wehy your results do not look as expected.  In order to 'help' the Place and Route phase of the Quartus tools achieve the results you desire, you will need to place timing assignments on your design. This is not doen wwith the TimeQuest timing analysis tool. You specifiy the desired clock frequency, and the Desired inout and output delays on and off chip as a minimum. There is a good Free Online training on the subject on the Altera WEB site under training.  TimeQuest can save an .sdc file, which you add to your design as a design input file, and then you place and route the design and inspect reports to see if you have met all 'requested' timing.  Then you can runt hte Timing Simulation and all should be good.  Enjoy.

[Altera_Forum]

Avatar: 

 I added output pins to look at internal signals, but they don't usually show up when I run simulation.  I choose view, utilities, then nodes, list all, then select all, then close that box. This should include all inputs and outputs show up on the timing chart.  Which tool should I run next to make sure that the last pins I added will be included in simulation?  Oh, BTW, what does it mean when the timing chart shows hash marks superimposed onto the expected output wave form? No white space where there should be ones and zeroes.

[Altera_Forum]

No commment on the 3 first statements / questions. 

 As regards the hash marks, this usually means that in the simulation the value is unknown (to the simulator).  This is usually because some reset signal or established value has not occured or propogated throught the logic in the design and the value (in the simulator) cannot resolve to a known level of 1 or 0.

[Altera_Forum]

Also the hashed white line would indicate that you are driving a "weak" high or low signal. If you move your cursor over the signal where the white hashed line is then the simulater window will show a 'H' or 'L' signal. 

 Regarding you timing simulation you will need to make sure that once the SDF is back annotated onto the netlist which is done something similar to the following  vsim -t ps -sdftyp tb_top/top_blk/=../../TOP/NETLIST/TOP_vhd.sdo TOP_TB_LIB.tb_top  the clock from the testbench should not be edge-aligned with the data as this would not satisfy the set-up requirement of the flip-flops and 'X' 's will be propagated in your design  Hope this helps

[Altera_Forum]

One thing I wanted to add to this thread - First, if you don't have timing requirements in your design, I suggest adding them. It's not necessarily what is wrong between the simulations, but this is a recommended step for all designs(constraining them). Without constraints, the fitter doesn't know what to do, and more importantly, there is no way for the back-end timing analysis to let you know if you passed or failed your requirements, since there are no requirements to begin with. 

 Second, although it's useful to understand the differences between a functional and timing simulation, I wouldn't try to fix the problem yet without diving deeper into why your timing simulation is failing. It can be a painful process, but at some point there is a register transfer where you expect something to happen, and something else happens. Once you find this, you can analyze why this didn't occur(is there an error in my code? Is the datapath too long for my clock rate? Etc.) Although it takes time to isolate the issue like this, it makes the fix much easier since you have a solid understanding of what you're trying to fix.

[Altera_Forum]

Hi ,Rysc.Thank you very much. 

You're all right. There do exist some problems in my project. I designed a random-phase clock management. There are five parts in my designs, the first part ,an N divider and a dff,it provides the clk needed in native circuits; the second one,a phase detector,it detects clk's rising event and data' falling event when data'phase is in front of clk',otherwise when clk'phase is forward,it detects data's rising event and clk' falling event ,then the detector sends the signal to the third part---a counter. The system provides global clk to the counter ,and then counter will send the number to a comparator ,which has been set an initial number(N/2),it provides three typical signals to first part and control the native clk(add or deduct one global clk circle) I examined my projects ,the problem may exist in second part.There are two parts ,datalate and databefore ,they all contain two dff, i use the clk'rising event to sample the data'rising event and use the data'rising event to sample the clk'rising event.

[Altera_Forum]

The circuitry you're describing concerns me in that it will be difficult to do static timing analysis on. Note that I would generally recommend to: 

1) Not do gated clocks, i.e. divide them down and use ripple clocks. Instead use a PLL to divide the clock down or use the higher speed clock and have your logic create clock enables rather than higher speed clocks. Ideally you want to have as few clocks as possible, and keep them edge aligned(all outputs of the same PLL or based off a single base clock), so you don't have to worry about hold analysis. 2) I wouldn't use the asynchronous ports of the register to perform logic. Instead, they should just be used as a system set/reset. Note that these are recommendations. Plenty of designs have broken these recommendations and work perfectly fine, but I find that often users do these things when they never really had to, and they find themselves unable to do static timing analysis(mainly because they don't understand how to constrain it). I've found these rules get broken more often than not in schematics because it's easy to do. Something happens on the output of a register and you want that signal to allow some other register to do something. So you tie it to the clock or asynch port of that register, rather than the clock enable. I know you don't want to go back and redo the design, but I'm just throwing these out there as a possibility.