Help:How to assign the ports?

[Altera_Forum]

As the timing analyzer picture shows ,how to assign the ports ?clk ,inst12,or others? 

I know the minimum slack time is not met ,but what and how can i do next? Please help me,thank you very much!

[Altera_Forum]

One of the possible causes of clock hold violations is flagged by the Classic Timing Analyzer compilation message below. If you got that message, see my posts at http://www.alteraforum.com/forum/showthread.php?t=754. 

   --- Quote Start ---  Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  --- Quote End ---  

[Altera_Forum]

Thanks ,Brand. 

After reading your thread, i understand something deeply, especially time constrain. Also your recommendation very good. I don't know them before, thanks very much again. Now i have a new problem needed to address. That is how to constrain and set the Quartus when the classic timing analyzer and the time-quest analyzer. The device i use is Max EPM1270F256c5, when i use classic one, i set the time-driven compilation as all path; i don't constrain the Tst,Tpd,Tco,and Th; the ports i set in assignment editor have many choose,etc. "Not a clock" "clock setting" "Auto global clock" and so on, i only know some of them,still many constrains are unknown, what material can i see? When i use The time-quest one, i just constrain the ports in assignment editor, is there any constrains i still need to? The time constrain really bother me, i know it not easy to do for a beginner like me. Maybe my question is naive ,but i want to make it well done! Thanks very much ,everyone!

[Altera_Forum]

You need to start by reading the relevant documentation. 

 Read through chapters 6, 7, and 8 in the Quartus handbook, Volume 3, Section II. Those chapters cover the Classic Timing Analyzer, TimeQuest Timing Analyzer, and a comparison between the analyzers. You don't have to understand everything in those chapters. Look through them to get a basic familiarity with what is available, and read carefully the parts that look most likely to be relevant to your present needs.  There are on-line demos, training, and design examples. For the Classic Timing Analyzer, start at http://www.altera.com/support/software/quartus2/timing/sof-qts-timing.html. For TimeQuest, start at http://www.altera.com/support/software/quartus2/timequest/tq-spt-index.html.  For each particular assignment in the Assignment Editor, look for an on-line help page for that assignment. You can usually find the help page by typing the assignment name exactly in the Help Search tab.  To be proper for any design, even a MAX II design, you should constrain all paths including I/O. However, there are many assignments in the Assignment Editor that you don't need on every design.  TimeQuest does not use any information from the Assignment Editor. It gets its constraints from an SDC file.  Don't be overwhelmed by the amount of information. Start by focusing on what you obviously need to know now.

[Altera_Forum]

Thanks very much, Brand. 

I have read the Quartus handbook, Volume 3, Section II carefully today. Now i know the TimeQuest Timing Analyzer much better than before. There are still something i don't understand.  I have set the constraints in the TimeQuest Timing Analyzer, after full compiling ,the TimeQuest Timing Analyzer summary shows some unconstrained paths, such as "Unconstrained Input Port Paths","Unconstrained Output Ports "and "Unconstrained Output Port Paths". You know that the constraints in the TimeQuest Timing Analyzer have clock sets, input and output delay sets, min and max delay sets, and so on. I have just constrained the clock,do i need to set other constraints and what do the constraints mean i need to set? In my work, i use some DFF and the clock of the dff is other asynchronous signals provided by logic cells , and i get the warnings say that the clock of the dff is not constrained when i set constraints, so i created clock and set the targets to the clock of dff ports ,then the warning disappeared, is it wright that i constraint them as clock? I don't think it is wright ,but the warning gone, why? I change the file.sdc to another one which has different constraints, actually,more constraints, the waveform is wrong. In a project ,what's the standard of the constraints? Hope you can help me .  Thanks very much. Regards.

[Altera_Forum]

--- Quote Start ---  I have set the constraints in the TimeQuest Timing Analyzer, after full compiling ,the TimeQuest Timing Analyzer summary shows some unconstrained paths, such as "Unconstrained Input Port Paths","Unconstrained Output Ports "and "Unconstrained Output Port Paths". You know that the constraints in the TimeQuest Timing Analyzer have clock sets, input and output delay sets, min and max delay sets, and so on. I have just constrained the clock,do i need to set other constraints and what do the constraints mean i need to set?  --- Quote End ---    It is recommended to use set_input_delay and set_output_delay -max and -min for all device pins (ports). You can instead use set_max_delay and set_min_delay, but those are not the preferred constraints for I/O. Chapters 6 and 7 cover this.     --- Quote Start ---  In my work, i use some DFF and the clock of the dff is other asynchronous signals provided by logic cells , and i get the warnings say that the clock of the dff is not constrained when i set constraints, so i created clock and set the targets to the clock of dff ports ,then the warning disappeared, is it wright that i constraint them as clock? I don't think it is wright ,but the warning gone, why?  --- Quote End ---    "...the clock of the dff is other asynchronous signals provided by logic cells..." sounds like you are using a ripple or gated clock. That is usually a bad idea. What you said about the warning going away makes me think it is a ripple clock.  If you are driving a register's clock input with anything other than a direct connection to a device pin or PLL, see my posts at http://www.alteraforum.com/forum/showthread.php?t=754. The thread is particularly about divided-down clocks, but the information applies to any ripple or gated clock. Some of the information there is about the Classic Timing Analyzer, but all the design guidelines and cautions apply to either analyzer. The main difference with TimeQuest is different reporting of an unconstrained ripple clock (a clock driven by a register) and no message about gated clocks (clocks driven by combinational logic).