Linking of two FPGA

[Altera_Forum]

Hi all, 

I'm a student of Engineering of Telecommunications.In my thesys I must realize a digital circuit on FPGA,but I can't make it all on the same FPGA board,because of occupation of resources.So I must realize some blocks of this circuit(such as a FIR filter) on a second FPGA board. Someone can tell me how could I connect a single block of the first FPGA with a block of the second one? Thanks in Advances.

[Altera_Forum]

Technically, you can connect FPGA's anyway you want. SPI, I2C, PCI, PCI Express, LVDS, DDR, etc. (I know I'm confusing protocol standards with IO standards and what not...) My guess is you're not designing the board, and the decision is probably already decided for you, at least at the physical layer. What type of physical connections are there between the boards? Once you have that, you need to decide how they interact? Do they need to send data back and forth within a clock cycle, or is it purely a data dump from one side to the other? Do you need any sort of error correction/protection, in case the wires get noisy? 

 My guess is it will be as simple as possible, whereby you connect as many wires as you physically can, depending on how much data you'll be sending, and then just send one bit of data per clock, assuming the clock speed is slow enough and there is a relationship between the clocks on the two FPGAs.

[Altera_Forum]

I agree with Rysc. Start with what interface is available on board for connecting two boards (and hence two FPGAs). Then look for what will be the maximum data transfer rate (and hence clock rate) required to meet the design requirements. If the board-to-board interface options meet your data transfer rate requirements then you can select any of the protocols to implement FPGA-to-FPGA communication. E.g., if it's a slow speed connection, you can use UART using two data lines + GND only to communicate between two FPGAs. If you need high speed, then you can use LVDS or some other tranceivers with standard or custom protocol, provided the board and the FPGA supports it.

[Altera_Forum]

Hello there, 

I have a similar problem pertaining two FPGAs together. Currently, my design has exceeded my FPGA's LE count and therefore, i am planning to connect two altera UP2 boards using JTAG. The UP board has a CPLD (EPM7128) and FPGA (Flex 10k).    from my understanding, if Quartus detected the assembly is larger than the device, it will generate more than one programming file..such as pof_1. However, the web edition software could notgenerate more than one program file. Instead, i have this error:   *** Error: Project requires 6182 logic cells, but the selected device can contain only 3744 logic cells Error: Can't find fit Error: Quartus II Fitter was unsuccessful. 2 errors, 1 warning  Info: Allocated 180 megabytes of memory during processing  *** Could it be my web edition quartus's limitation?

[Altera_Forum]

Quartus II won't ever generate two programming files from one design. There are a number of issues(how do we know the pinout of the second device is the same as the first, and even if it is, which pins do we use? Transferring data between devices will add cycles/delays, which will change the functionality. Plus splitting a project at a given place generally adds a lot of other pins we would need to connect, etc.) These issues all need to be handled by the user, i.e. create two separate projects with separate code, and develop a way for them to talk to each other.

[Altera_Forum]

Hi, 

 I have heard of "super-project" (or some terminology like that) feature in Quartus for multiple fpgas but never went for it.

[Altera_Forum]

Max+Plus II used to be able to do that ~10 years ago, but it didn't really work. It almost always split in a way that required way too many pins(devices back then didn't have a lot, and most blocks have quite a few nets going between hierarchies, so it's still a problem now). You would also need a horribly slow clock speed since you would be sending data across chips(and with combinatorial logic in the path) at the clock rate to keep them within a cycle. 

Synplicity Certify(I think that's the one) has some very cool features for doing this, although it's still usually somewhat manual. It's far from free though, and I think is targeted for ASIC prototyping.

[Altera_Forum]

thanks for the feedback. . 

 if i use single core wires to connect the quartus FPGAs..anyone knows of a typical clock cycle rate? cause my ALU is suppose to do something every posedge clock.  good luck to me....

[Altera_Forum]

Obviously it depends on your PCB technology but to give you my current maximum PCB figure: I use 153.6MHz between my stratix ii and an SDRAM(32 bits bus) without problem.

[Altera_Forum]

Propagation time can be found from one of the info messages... 

 Info: Longest tpd from source pin "out[0]" to destination pin "LED[3]" is 35.600 ns

[Altera_Forum]

Question: There was a general rule that electrical signals take 1ns to travel 15cm... But why interconnect time reported in Quartus typically in around 5ns..sometimes even more? arent the interconnects in micrometers? i am worried because i am using ribbon cables to send data to a second board.. and common sense tell me their propagation time will be much more than the time taken between LE interconnects in FPGA.

[Altera_Forum]

On your previous post, a Tco of 35.6 seems really long, but you should be using static timing analysis(TAN or TimeQuest) to analyze it further, not just the info message. If it's an old process or there's a lot of logic, it's certainly possible. 

Timing inside a device is considerably different than externally. The drive strength of the internal transistors, the capacitive loading, etc. all make a difference. I wouldn't try comparing the two.

[Altera_Forum]

--- Quote Start ---  thanks for the feedback. .  if i use single core wires to connect the quartus FPGAs..anyone knows of a typical clock cycle rate? cause my ALU is suppose to do something every posedge clock.  good luck to me....  --- Quote End ---    i once used 50Mhz(slow) as the clock rate by dividing my board clock and it was working.