bidirectional pin simulation for serial I2C

Altera_Forum · ‎09-20-2007

I have problems with bidirectinal pin simulation for serial comunication,

problem is there that simulator didn't show writes to SDIO inout pin and also don;t show read from this pin

I created test software wear I write some data to parallel-serial converter which sends serial data to SDIO pin and at the same time second logic-> serial to parallel converter reads data form SDIO line and show result, to show that parallel-serial logic work I inserted aditional output signal S_ouT were I can see that all is working, but on SDIO and SDIO~result are no signals.

how to set up this inout signal ??

here is .vwf file

https://www.alteraforum.com/forum/attachment.php?attachmentid=189

and here is simulation result

https://www.alteraforum.com/forum/attachment.php?attachmentid=188

I also read previous topic where was about bidirectional IO simulation but there was no useful information, I also read quartus handbook about simulating bidir IO and did all I can, but no results.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPI_test is
  port(clk,LD,Ren,OE  : in std_logic;
		Data : in std_logic_vector( 7 downto 0);
       SCK : out std_logic;
		SDIO : inout std_logic;
	parallel_out : out std_logic_vector( 6 downto 0);
	T_enT,LD_T,S_ouT : out std_logic
		);
		
end SPI_test;
architecture SPI_test_arhitektura of SPI_test is
 signal timer,tmp :STD_logic_vector (7 downto 0);
	signal Timer_parallel : std_logic_vector ( 2 downto 0);
	signal Rdone,Timer_start, Timer_end, T_en,t_end, sdio_out, 
	sdio_in : std_logic;
component serial_paralel is
  port(CLOCK_16,Ren, SDIO  : in std_logic;
	parallel_out : out std_logic_vector( 6 downto 0));
end component;
begin 
process(clk)
begin
if rising_edge(clk) then
	if LD ='1' then 
tmp <=data;T_en<='1';
	else tmp(7 downto 1)<= tmp(6 downto 0);
	 end if;
end if;
end process;
Sdio_out<=tmp(7);  -- serialsignal that gows to bidir IO
S_ouT<=tmp(7);   -- Test signal for serial output
--Altera code for Bidir IO setup
PROCESS (oe, SDIO)          -- Behavioral representation 
   BEGIN                    -- of tri-states.
        IF( oe = '0') THEN
			SDIO <='Z';
            sdio_in <= SDIO;
        ELSE
            SDIO <= sdio_out; 
            sdio_in <= SDIO;
        END IF;
    END PROCESS;
-- serial-parallel logic code block initialization
Serial_in : serial_paralel 
  port map(CLOCK_16=> clk,Ren=>Ren,SDIO=>SDIO_in,parallel_out=>parallel_out);
end SPI_test_arhitektura;

Altera_Forum · ‎09-21-2007

I just tested this bidir pin code on my cyclone II dev.kit and it looks like bidirectional IO works, but simulator still don't work.

I think I will use for testing separate single output pin that will show oputput signal.

Altera_Forum · ‎09-27-2007

Hi Epis,

IMO problem is that VHDL simulator can't handle the 'Z' state. In real world , I assume that your SDIO pin is pullup'ed. There is a way to simulate this behavoiur in VHDL, you should use 'H' state (instead of 'Z') , which stand for 'Weak one' . The VHDL resolution function will then , for example, handle the case where an external '0' is applied on your SDIO 'H' state : in this case, the result would be '0'.

More help here : http://www.csee.umbc.edu/help/vhdl/misc.html

I used this to simulate an I2C bus transaction (SDA and SCL are also bidir lines), it works nice, at least using Modelsim simulator.

Warm regards.

Altera_Forum · ‎09-28-2007

For me it is strange, that you perform read and write to SDIO at the same time. I was using bidirectional pins. VHDL description looks like this:

IO <= output when OE = '1' else (others => 'Z');

Controlling the OE signal you can change the direction of IO pin/bus. As for simulation, you can observe data out , but reading from IO is practically impossible.