rams in Quartus

[Altera_Forum]

Hi,everyone. 

I want to use ram in my design. I find some types in Quartus. I don't know what's the detailed differences among them and how to use them, such as how to initialize them.For example, "lpm_ram_dq" , I create it and leave it blank, now i want to use it , how to write " _.mif " to it , can it ? or I have to initialize it when i create it?:confused:   Thanks everyone!

[Altera_Forum]

hi, 

 i asume you want to use the on chip memory.  first, the lpm rom/ram functions are not to be used any more. you choud use the altsyncram object. The mif files are louded in to the ram cels(m4k, m9k,...) at configuration time, they are compiled in to the sof or the pof file. these files can be etided via the quartus interface.  Reading and writing is very easy, the data is stored or writen to (depends on wren ) wen the block get its clock signal.  Here is a link where you can find al the info needed http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf  hope this helps you out.

[Altera_Forum]

Thanks mirimon. 

I have found the stuff i need in the pdf. Why does "the lpm rom/ram functions are not to be used any more" ? Any disadvantage or inconvenience?

[Altera_Forum]

I'm using the mif to initialize the mem in the pof for our firmware, 

this is working great on stratix 2 fpga !

[Altera_Forum]

--- Quote Start ---  Thanks mirimon. I have found the stuff i need in the pdf. Why does "the lpm rom/ram functions are not to be used any more" ? Any disadvantage or inconvenience?  --- Quote End ---   hapyang, In Quartus II MegaWizard plug-in Manager, Memory compiler section, choose the memory type you want to implement. The .v or .vhdl file written out will show you what function is instantiated - lpm or alt function. Quartus II takes care of it for you.   lpm rom/ram functions are not an inconvenience but those are legacy functions for older generation device families.   For further reading, you may want to look into 1) http://www.altera.com/literature/ug/ug_memrom.pdf  2) www.altera.com/literature/ug/ug_ram.pdf

[Altera_Forum]

Start with 

http://www.altera.ru/disks/altera%20documentation%20library/literature/an/an307.pdf (http://www.altera.ru/disks/altera%20documentation%20library/literature/an/an307.pdf)  Stefaan

[Altera_Forum]

I think, embedded RAM functionality is similar to Xilinx but not identical. Comparing the RAMB4_S16_S16 primitive with altsyncram Megafunction with appropriate parameters, I see two differences:  

1. RST(A/B) is a synchronous clear while altsyncram has an asynchronous clear option. 2. RAMB4_S16_S16 has initialization in generics while altsyncram uses *.mif or *.hex file  There may be additional functional differences, but the altsyncram port signals can be parametrized to equal RAMB4_S16_S16 as far as I understand. If your application doesn't depend on synchronous clear for the output registers or initialization in generics, you can write a wrapper that emulates RAMB4_S16_S16 through altysncram.

[Altera_Forum]

You can define a RAM module in Megawizard with properties equal to RAMB4_S16_S16.  

 You would get a component definition like this component altRAMB4_S16_S16 PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock_a : IN STD_LOGIC ; clock_b : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0); enable_a : IN STD_LOGIC := '1'; enable_b : IN STD_LOGIC := '1'; wren_a : IN STD_LOGIC := '1'; wren_b : IN STD_LOGIC := '1'; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); end component;  In the wrapper architecture, you instantiate this module using the RAMB4_S16_S16 port names: RAMB4_S16_S16_inst : altRAMB4_S16_S16 PORT MAP ( address_a=> ADDRA, -- Port A 8-bit address input address_b=> ADDRB, -- Port B 8-bit address input clock_a => CLKA, -- Port A clock input clock_b => CLKB, -- Port B clock input data_a => DIA, -- Port A 16-bit data input data_b => DIB, -- Port B 16-bit data input enable_a => ENA, -- Port A RAM enable input enable_b => ENB, -- Port B RAM enable input wren_a => WEA, -- Port A RAM write enable input wren_b => WEB, -- Port B RAM write enable input q_a => DOA, -- Port A 16-bit data output q_b => DOB -- Port B 16-bit data output ); In the wrapper entity, you export the RAMB4_S16_S16 port names. You could shorten this action by simply renaming the ports in the wizard generated designfile, but then it could be no longer edited by the Megawizard.

[Altera_Forum]

You can instantiate the example altRAMB4_S16_S16 also in Verilog. I skipped the step of creating a wrapper module and instantiated the Megawizard generated module directly instead of original RAMB4_S16_S16. You could omit some unused signals, as the port specific clock and the enables, that I used to be compatible with RAMB4_S16_S16 definition. 

altRAMB4_S16_S16 mem ( .address_a (ADDRA), .address_b (ADDRB), .clock_a (clk), .clock_b (clk), .data_a (DINA), .data_b (DINB), .enable_a (1'b1), .enable_b (1'b1), .wren_a ( WE), .wren_b ( WE), .q_a (DOUTA), .q_b (DOUTB) );

[Altera_Forum]

I included a Wraper instead of editing your file and the design could be compiled. 9 RAM blocks had been used. Of course I couldn't easily check the design for correct function.

[Altera_Forum]

The error is due to the fact, that you didn't include the previously posted altRAMB4_S16_S16.v to your design directory, which contains the Megwizard generated RAM. The wrapper references this design file, as you easily can see from the text.

[Altera_Forum]

You may also want to look at the Quartus II templates under Edit -> Insert Template. The Full Designs category has a sub-category for inferred RAMs and ROMs. I prefer to infer when I can and instantiate a megafunction when I must. The software will automatically create a MIF to model the initial contents specified by your HDL. However, the Update Memory Initialization File feature doesn't work with inferred RAMs as far as I know. That is, you can't edit the auto-generated MIF and invoke this feature to update the programming file with the new memory contents. You must edit your HDL and recompile.