A source synchronous interface is one where clock and data are sent together and the transmit clock is used to capture the data at the receiver. This paper will focus on timing analysis using ALTLVDS transceivers (not GPIO), which only exist in the Stratix family of FPGAs.
The methodology required to analyze ALTLVDS timing will be shown in the first section. The second section will touch on the problem of trace mismatch. The last section will focus on using the Quartus II TimeQuest Timing Analyzer and Classic Timing Analyzer (TAN) to analyze timing.
