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When I first tried to run the generated testbench (of my Viterbi decoder), I kept getting undefined numerr, despite the fact that my input signal has 3dB SNR. (I have attached my top HDL wrapper for my Viterbi decoder).
It took me a while to figure this out. However, it seems like the ber_clear signal isn't connected properly in the generated testbench. To fix it, I had to add the following two lines: At line 137: ber_clear : out std_logic; At line 268: ber_clear =>ber_clear, I am not sure whether this applies to just some or all Viterbi case (when BER is selected), but thought it would be good to share with y'all anyways. I have attached: (1) The top level HDL wrapper for my Viterbi module. (2) My modified testbench.Link Copied
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