FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Viterbi 7.2 - numerr behavior

Altera_Forum
Honored Contributor II
1,186 Views

I spent quite some time figuring out what 'numerr' does in the case of "continuous" optimization of the viterbi decoder module in the IP Toolbench. I thought I would share my experience with you guys. 

 

In this case (continuous Viterbi), the Toolbench generates a viterbi module with 'numerr' output wide enough to accommodate whatever size is chosen for "Number of Bits Per Block". However, the documentation is not exactly clear on numerr's behavior when it exceeds the predetermined size...  

 

Long story short: Numerr simply rolls back to zero once it exceeds the size of "number of bits per block".  

 

It was impossible to see that from the provided testbench, so I created my own testcase in DSP Builder (version 7.2). In this case, a Bernoulli sequence is convolution encoded and decoded with Altera's Viterbi decoder. The good case is included with this post (I thought it showed a unique way to interact Simulink blocks with Altera's blocks).  

 

P.S. To see numerr's behavior, I simply reversed the encoded bitstream to see the numerr behavior.
0 Kudos
0 Replies
Reply