MAX10 Dual port RAM compiler - memory not working in silicon

[Altera_Forum]

Dear all, 

 I'm using an Intel® MAX® 10 FPGA Development Kit (MAX10M50DAF484C8G), trying to implement a dual port RAM in Quartus 17.0.  No way to have it working.  I tried several options, always reaching the end of configuration correctly but none worked (with/without byte enables, 1 clock or separate ones, different sizes, registered/non reg. outputs etc.)  When I used - just for test - a simple ONE port RAM it worked.  Does anyone managed to have a true dual port RAM working on a MAX10M50DA?

[Altera_Forum]

Did you write code to do this or are you using something from the IP Catalog? If it's code, post it here so we can see what you are trying to do.

[Altera_Forum]

--- Quote Start ---  Did you write code to do this or are you using something from the IP Catalog? If it's code, post it here so we can see what you are trying to do.  --- Quote End ---    The reason why I asked if someone managed to work with a DUAL port ram instantiation in MAX10DA: for me that would assure it's me to dig better. If noone did, I think there is an issue with compiler (same code worked for a similar grade in Xilinx, apart from RAM IP).  --> Please note that I had to update IP for memories (red flag) ...  Anyhow answer to your question is:   --> I use IP Catalog, RAM2p, please find it in attach.  Kind regards, Federico