Custom Component with parameters to define signal width

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I'm using SOPC Builder 7.1 to create a custom component. 

The entity shows below:  LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL;  ENTITY FREQMeasure_AvalonSlave IS generic ( GEN_TOTAL_CHANNEL : integer := 360; GEN_BENCHMARK_FREQUENCE : integer := 5000;--KHz GEN_MAX_TARGET_FREQUENCE : integer := 100;--KHz GEN_T_STROBE_PERIOD : integer := 8; --MicroSecond GEN_T_STROBE_WIDTH : integer := 4 --MicroSecond );  port ( --Signals for Avalon-MM slave port "s_FREQMeasure" --input  avs_FREQMeasureInterface_clk : IN STD_LOGIC;  avs_FREQMeasureInterface_reset_n : IN STD_LOGIC; avs_FREQMeasureInterface_read : IN STD_LOGIC; avs_FREQMeasureInterface_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); avs_FREQMeasureInterface_export_IN_TargetClk : IN STD_LOGIC_VECTOR(GEN_TOTAL_CHANNEL - 1 DOWNTO 0); --output  avs_FREQMeasureInterface_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) );  END FREQMeasure_AvalonSlave;   parameter GEN_TOTAL_CHANNEL is used to define width of export ports: avs_FREQMeasureInterface_export_IN_TargetClk   After creating the component in component editor of SOPC Builder, and then instance the component(with GEN_TOTAL_CHANNEL = 10) in NiosII system, then generate the system.  Finally, I use the symbol of NiosII system in *.bdf file, but I found that the width of avs_FREQMeasureInterface_export_IN_TargetClk was 1 and not 10 expected.   Pls see the attachement for the pic of symbol.  All the information I have is only the following information: The following rules apply to HDL parameters exposed via the component GUI: ■ Editable parameters cannot contain computed expressions. ■ If a parameter N defines the width of a signal, the signal width must be of the form N-1..0. ■ When a VHDL component is used in a Verilog system module, or vice versa, numeric parameters must be 32-bit decimal integers. Passing other numeric parameter types might fail. Click Preview the Wizard at any time to see how the component GUI will look to an end user.   P.S. The *.tcl created is showed below: # TCL File Generated by Component Editor on:  # Mon Dec 03 16:19:35 CST 2007 # DO NOT MODIFY  set_source_file "FREQMeasure_AvalonSlave.vhd" set_module "FREQMeasure_AvalonSlave" set_module_description "" set_module_property instantiateInSystemModule true set_module_property version "1.0" set_module_property group "CWG" set_module_property editable true  # Module parameters add_parameter "GEN_TOTAL_CHANNEL" "integer" "360" "1-512" add_parameter "GEN_BENCHMARK_FREQUENCE" "integer" "5000" "KHz" add_parameter "GEN_MAX_TARGET_FREQUENCE" "integer" "100" "KHz" add_parameter "GEN_T_STROBE_PERIOD" "integer" "8" "ms" add_parameter "GEN_T_STROBE_WIDTH" "integer" "4" "ms"  # Wire Interface global_signals_export add_interface "global_signals_export" "conduit" "output" "asynchronous" # Ports in interface global_signals_export add_port_to_interface "global_signals_export" "avs_FREQMeasureInterface_export_IN_TargetClk" "export"  # Clock Interface FREQMeasureInterface_clock add_clock_interface "FREQMeasureInterface_clock"  set_interface_property "FREQMeasureInterface_clock" "externallyDriven" "false" set_interface_property "FREQMeasureInterface_clock" "clockRateKnown" "false" set_interface_property "FREQMeasureInterface_clock" "clockRate" "0" # Ports in interface FREQMeasureInterface_clock add_port_to_interface "FREQMeasureInterface_clock" "avs_FREQMeasureInterface_clk" "clk" add_port_to_interface "FREQMeasureInterface_clock" "avs_FREQMeasureInterface_reset_n" "reset_n"  # Interface FREQMeasureInterface add_interface "FREQMeasureInterface" "avalon" "slave" "FREQMeasureInterface_clock" set_interface_property "FREQMeasureInterface" "isNonVolatileStorage" "false" set_interface_property "FREQMeasureInterface" "burstOnBurstBoundariesOnly" "false" set_interface_property "FREQMeasureInterface" "transparentBridge" "false" set_interface_property "FREQMeasureInterface" "readLatency" "0" set_interface_property "FREQMeasureInterface" "readWaitStates" "1" set_interface_property "FREQMeasureInterface" "isFlash" "false" set_interface_property "FREQMeasureInterface" "holdTime" "0" set_interface_property "FREQMeasureInterface" "printableDevice" "false" set_interface_property "FREQMeasureInterface" "registerIncomingSignals" "false" set_interface_property "FREQMeasureInterface" "readWaitTime" "1" set_interface_property "FREQMeasureInterface" "setupTime" "0" set_interface_property "FREQMeasureInterface" "addressGroup" "0" set_interface_property "FREQMeasureInterface" "interleaveBursts" "false" set_interface_property "FREQMeasureInterface" "addressAlignment" "DYNAMIC" set_interface_property "FREQMeasureInterface" "isBigEndian" "false" set_interface_property "FREQMeasureInterface" "writeLatency" "0" set_interface_property "FREQMeasureInterface" "writeWaitTime" "1" set_interface_property "FREQMeasureInterface" "timingUnits" "Cycles" set_interface_property "FREQMeasureInterface" "minimumUninterruptedRunLength" "1" set_interface_property "FREQMeasureInterface" "registerOutgoingSignals" "false" set_interface_property "FREQMeasureInterface" "addressSpan" "16384" set_interface_property "FREQMeasureInterface" "isMemoryDevice" "true" set_interface_property "FREQMeasureInterface" "linewrapBursts" "false" set_interface_property "FREQMeasureInterface" "alwaysBurstMaxBurst" "false" set_interface_property "FREQMeasureInterface" "writeWaitStates" "1" set_interface_property "FREQMeasureInterface" "maximumPendingReadTransactions" "0" set_interface_property "FREQMeasureInterface" "wellBehavedWaitrequest" "false" # Ports in interface FREQMeasureInterface add_port_to_interface "FREQMeasureInterface" "avs_FREQMeasureInterface_read" "read" add_port_to_interface "FREQMeasureInterface" "avs_FREQMeasureInterface_address" "address" add_port_to_interface "FREQMeasureInterface" "avs_FREQMeasureInterface_readdata" "readdata"  Anyone help! Thanks in advance...