DSP Builder and Signal Tap II

[Altera_Forum]

Hi,  

 I have some simple questions.  I working on an Altera DE2 with a Cyclon II FPGA inside.  I'm doing some simulation with the DSP Builder like simulate a stair signal ora a Sinewave signal and catching it with the Signal tap.  I'm in trouble with the clock I think.  1)To set the real clock of the board I have to use the clock block obviously...but..anithing else? Should I have to make a PIN assignement? (with the pinout assignement block?)  2) If the signal is too slow maybe the max 8k of samples of the Signal Tap are not enough to see something concrete, so I 've decided to use a derived clock to clock the signal tap slower. Everything is good till I start the data acquisition: the acquisition doesn't stop and I have to turn off the board   Any help? Any idea? THANK YOU

[Altera_Forum]

Hi, 

 (1) You will have to make PIN assignments. However, the best way is to include the Cyclone II DE2 board block (can be found under board blocks in version 7.2). If you double click on that block, you will realize that all pin assignments were made for you already. That would probably save you a lot of trouble.   (2) I believe your problem is due to the lack of pin assignments. I haven't had a problem seeing signals with SignalTap (however fast or slow).  Hope this helps!

[Altera_Forum]

I've just put my DE2 board block in the schematics, so are there no other assignements to do more then the ones in the board block? Also if I use the clock block? And also if I use the clock derived block? 

 I think to have solved the problem anyway. I think that the problem was in using a derived clock for the signal tap so I 've used the base clock for the SIgnal Tap and I've speeded up the simulation with a PLL clock.  The manual is not really clear about PIN assignement and clocks...

[Altera_Forum]

Hello, 

 using a derived clock for Signal Tap most likely causes timing problems und incorrect signal acquisition. Anything that is said regarding not to use derived clocks in design also applies to Signal Tap. Signal Tap should be clocked by the design's under test main clock. A PLL generated divided or multiplied clock can also give good results. "Acquisition doesn't stop" sounds like there is no real clock at all. A simple way to get a slow signal tap aquisition is with a derived clock as trigger for segmented x 1 acquisition mode, but you don't have another trigger then and can do only free-running acquisition.  Regards,  Frank

[Altera_Forum]

Thanks, I will tray also your way.

[Altera_Forum]

Hi all, 

Sorry but I don't understand the workarounds at all :( I have similar problem, I try to check correction of data from audio codec with signaltap on 2S60 DK. How can I decrease rate of data assigns to signaltap memory. Thank you in advance. yan_w

[Altera_Forum]

The discussion has been regarding requirements for a suitable acquisition clock. It's not said, that you can't use a gated clock at all. It may work, although the timing is probably not perfect. I often use it as a quick and dirty solution. Alternatively you can use segemented trigger to acquire data at a reduced rate. If I understand right, Quartus 8 has new options in this regard, but I didn't evaluate them yet.

[Altera_Forum]

I put signaltap block before and after rasampling block at simulink and after acquisition I receive same data. 

How can I do it in dspbuilder if at all? Thanks again.

[Altera_Forum]

Sorry, I'm not familiar to this tools.

[Altera_Forum]

FvM 

Thank you for help. ;)