basic always block question

Altera_Forum · ‎01-02-2017

I have questions about always blocks. Both will use the following always block for context:


always @ (posedge Clk)
begin
if (x1)
    q <= 1;
else if (x2)
    q <= 0;
else
    q <= q;
end

where q, x1 and x2 are all 1 bit wide.

Would this code 'prioritize' checking x1 before x2? What would happen if x1 and x2 were both high?

How exactly would it synthesize?

Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?

Thanks

Altera_Forum · ‎01-02-2017

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Would this code 'prioritize' checking x1 before x2?

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Obviously yes.

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What would happen if x1 and x2 were both high?

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The same as only x1 high?

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How exactly would it synthesize?

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Any logic fulfilling the behavioral description would be correct. In FPGA as D-FF with preceding logic. You can watch the synthesis result in Quartus post synthesis net list.

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Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?

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The final else statement is redundant and can be omitted. A register keeps the previous state by default.