TimeQuest slides

[Altera_Forum]

There have been a number of posts on TimeQuest lately, and I thought I'd throw up some slides I put together that might be useful. It is assumed the user has played with TimeQuest a little, and understands the constraints(those topics are covered by other materials already.) This shows more of how the setup/hold paths are calculated, how default setup and hold requirements are calculated from clock constraints, and how multicycles affect those default setup and hold requirements.

[Altera_Forum]

I have read the ppt. 

Totally it should be a great presentation for midium & advanced user as well as newer.  But if you add some vivid & typical example related to real application, it will be more helpful for newer.   For me, could you give more information for the following words: As long as user is aware of caveats, set_max/min_delay can be useful Case# 1: Requirement is not related to clock edges Output Enable launch edge may have to switch at output before latch edge occurs to minimize bus contention Reduce metastability – If user has two registers for demetasabilizing a signal, they should transfer as quickly as possible. set_max_delay 1.0 can be used here  Question1: I think I never run into the first case, so I don't understand what you mean.(that is why I say if you add some vivid & typical example related to real application, it will be more helpful for newer)  Question2: Actually, In my current project, I use lots of synchronizer(containing two registers reg1&reg2 for demetasabilizing a signal), so basing on your presentation, I do the following constraint, does it right? set_max_delay -from [get_registers {|General_Synchronizer:*|reg1}] -to [get_registers {|General_Synchronizer:*|reg2}] 1   I will be very thankful if you can explain why If user has two registers for demetasabilizing a signal, they should transfer as quickly as possible

[Altera_Forum]

I has a real application question, pls see the following pic: 

http://blogimg.chinaunix.net/blog/upfile2/080123111343.jpg  How to constraint in TimeQuest for the requirement that： data_in arrive at DATA_A must be slower than clk arrive at DATA_B.  Thanks in advance!

[Altera_Forum]

Thanks for the comments. There's definitely a lot that could be added, and if I get the time I am thinking of adding direct examples. The set_min/max_delay slides were thrown in last minute, which is why they tend to be packed without good examples. But it's just too difficult to cover everything. For example, on the metastability one: 

 Metastability occurs when the data transitions within the registers setup/hold requirements. The register goes to an intermediate "unkown" state. If the data and clock are truly asynchronous, then there is no way to avoid this. In most asynchronous transfers like this, the user does not care if the register gets a 1 or a 0 on that clock, just that it clearly goes to one of those values. If it does not, it can cause problems downstream. The most common case is when the metastable register feeds multiple destinations. For example, if it fed two bits of a state-machine, one path might see that register's "unknown" state as a 1, the other register might see it as a "0", and the state-machine would go into an undefined state and perhaps never recover. Not good.  Now, a common practive is to double(or triple, etc.) register the asynchronous signal into the new domain. How does this help? The first register can go metastable, as it's input is asynchronous. A metastable register in an "unknown" state will eventually fall to a valid state, whether it be a 1 or a 0. The common analogy is that it is a rock on the top of a curve, which will eventually roll down to the 1 or a 0. This process has odds that it will go to a known state within a certain amount of time. For example, it may be 1/10,000 metastable events that will still be "unknown", or at the top of the curve, after 1ns. It might be 1/1,000,000 after 2ns. It might be 1/1,000,000,000,000 after 4ns. So if you wait 4ns before recapturing the signal, you can be pretty sure that the metastability will have shaken out and the second register will always be a known 1 or 0, over the lifetime of the product. (I'm making the numbers up so far, so don't trust them too closely. Also note that ever transfer won't cause metastability. For example, if the signal switches approximately every 20ns, and the receive register's Tsu/Th window is only 200ps, then ~1/100 transfers would go metastable. And usually these signals transfer much less than that.) Anyway, if our receiving double registers are driven by a 10ns clock, then we have a 10ns setup requirement between the two clocks. So let's say the fitter places and routes so the data delay is 9.999ns and it just makes timing. If the first register goes metastable and stays that way for 100ps, then that metastable condition will travel through 9.999ns of delay will be clocked into the second register. But if the user put a set_max_delay of 1.0ns on the path and it met timing, so the path was 1.0ns long between the double registers, then the first register could go metastable and have 9.0ns before it settles to a known state, at which point this known value would transfer to the destination register before it's latching clock, and the second register would never latch in the metastable event.  Admittedly, diagrams would help a lot with this, but hopefully that makes sense. Hopefully it also shows why there are a lot of examples, but by adding them all and properly explaining them, the presentation would get confusing and diluted(and that's assuming I had the time out of my normal job to take on such a task...) But keep asking questions.

[Altera_Forum]

To your diagram, don't design this way, as it's not synchronous. OUT_AD_SCLK is a clock that drives registers. It is preferable from a synchronous design standpoint to have CLK drive the CLK port of the registers currently driven by OUT_AD_SCLK and have DATA_A drive the clock enable port of those registers. You will have the same functionality, except your clock edges all line up, so you don't have to worry about hold violations and your setup requirements will be based on your clock period. Try to avoid gating clocks as much as possible. (There are conditions where it is required, but they take a lot more expertise, and far too often users gate clocks when they don't need to, which just causes problems later on.)

[Altera_Forum]

Now, I have understand why If user has two registers for demetasabilizing a signal, they should transfer as quickly as possible basing on your response. Thanks a lot. 

 But I don't understand why triple registers for demetasabilizing a signal will be better than double registers mode.  Could you answer my second post, either?  Thanks again!

[Altera_Forum]

--- Quote Start ---  To your diagram, don't design this way, as it's not synchronous. OUT_AD_SCLK is a clock that drives registers. It is preferable from a synchronous design standpoint to have CLK drive the CLK port of the registers currently driven by OUT_AD_SCLK and have DATA_A drive the clock enable port of those registers. You will have the same functionality, except your clock edges all line up, so you don't have to worry about hold violations and your setup requirements will be based on your clock period. Try to avoid gating clocks as much as possible. (There are conditions where it is required, but they take a lot more expertise, and far too often users gate clocks when they don't need to, which just causes problems later on.)  --- Quote End ---    Hi, OUT_AD_SCLK will drive external serial AD to output serial data which has no clock enable pin. So I think I have to use gate clock, the contraint I hope to do is to eliminate burr from the gate clock OUT_AD_SCLK.  Any suggestion?

[Altera_Forum]

Is the OR gate being used to turn the clock on/off(i.e. is DATA_A held at a level for long periods), or is it used to just slow down the clock(so DATA_A is a periodic function)? What is the clock rate of CLK? What rate do you want S_CLK_OUT to be? Right now you're going to have a runt pulse, most likely. For example, if the register is outputting a 1, DATA_IN is at 0, then when the clk goes from 0 -> 1, the S_CLK_OUT will go high momentarily(from the CLK path through the OR gate), but shortly after the register will toggle low and drive it low. So you'll get a short pulse. This may be acceptable at the A/D, but is it what you want? 

What device are you using? Is CLK on a PLL? If you have access to a PLL it makes it much easier. If just creating a slower speed clock, try to use another output of the PLL, or just divide down a register and have that go off chip(don't have a combinatorial gate being sent off chip as a clock.). If you're using the enable to turn the clock on and off(which usually isn't necessary for an A/D, I believe), then have the PLL output drive an ALTCLKCTRL megafunction. This is the mux used to get onto the global, so the PLL drives them anyway without being instantiated, but by manually adding it you have access to the enable port, allowing you to turn on and off your PLL output. (I can probably help more depending on your answers...)

[Altera_Forum]

--- Quote Start ---  Is the OR gate being used to turn the clock on/off？  --- Quote End ---   Yes! The s_ad_sclk_enable is work as a clock enable signal. s_ad_sclk_enable keep high normally, so that gate clock will output high also. Something will drive it to low and maintain 16 periods of clk, so that gate clock will output clk signal for 16 periods for reading AD data back. Pls see the following AD Timing diagram: http://blogimg.chinaunix.net/blog/upfile2/080124091830.jpg   The clk is generated from PLL directly and freq is 12.5MHz.

[Altera_Forum]

I would recommend: 

a) Adding a PLL output for this s_ad_clk, and have it drive an altclkctrl block. Then use the enable on this block to turn the clock on and off. This is a nice synchronous way to do it without glitching or anything.  b) If you don't want to use a toggle register, and your part has dedicated double-data rate registers in the IO, then instantiating the altddio megafunction and tie the two register inputs to 1 and 0. This way the DDR mux that is controlled by the clock just switches between selecting these two static outputs(i.e. it makes a clock) c) If you don't have an extra PLL output or global for this, then use a register to drive directly off chip(like a 24MHz toggle flip-flop) and drive the enable of that register to turn it on and off. This way there is no glitching.

[Altera_Forum]

for a: I have 120 AD channel, so the altclkctrl will be not enough. BTW, where can I find the info that how many altclkctrl blocks contained in selected device? 

 for b: I don't understand it. :(  for c: It should be the better way, I will give it a try.  Thanks.