i am trying to use up3 board to generate sound and having problem to connect the speaker to the fpga.i mean which port should i connect the speaker to on the board?:confused:
i am using verilog hdl which i get from
www.fpga4fun.com like below....
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module music(clk, speaker);
input clk;
output speaker;
// Binary counter, 16-bits wide
reg [15:0] counter;
always @(posedge clk) counter <= counter+1;
// Use the highest bit of the counter (MSB) to drive the speaker
assign speaker = counter[15];
endmodule
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thank you!!:) :)
