Will config done only be asserted after the very last byte in the RBF file is completely loaded for both uncompressed and compressed RBF files regardless of how slow DCLK is or how much time elapses between each byte?
In other words, is the RBF file guaranteed to only contain the exact number of configuration bytes?
Quartus 7.0 or later and Cyclone II and III devices.
For our HW, a PLD and FPGA are on the same bus but only 1 can be active at a time. During PS mode initialization the PLD that implements the PS load "steals" the FPGA address space. Once config done is asserted the PLD is disabled and once init done is asserted the FPGA controls the bus. We're trying to prevent a case where an extra pad byte is sent and either nobody responds or the FPGA erroneously responds.
Stefan
