Design begining phase..

[Altera_Forum]

Hi Friends... 

  Here in this forum we had been talking a lot about timing, multicycle path etc etc..bla bla bla.....   My doubt is, before we begin any design say 50 MHz, or 60 MHz or any thing, how we will get a rough idea that my design will run in that frequency. If we dont have an idea of rough frequncy of our target will run, its going to be a wilds goose chase, because once our design is coded and its not running...AAHHHHH... :( The company will come to ruins.  Plz share your views.  Regards freak

[Altera_Forum]

I assume, that you didn't want to rate the profound forum discussion as blah, blah. 

 You can use performance overview data given in the datasheet as a rough estimation what can be achieved. If you have already done FPGA designs, you'll probably know that in advance for a particular device family.  If you are new to FPGA design, you should realize critical parts of your design on an evaluation platform. You also try to judge from simulation only, if a design can be realized, but I wouldn't suggest it.

[Altera_Forum]

Hi. 

  FPGA data sheet tells only the max operating freq of that device.  Suppose i need to implement a protocol running at 100 MHz. How can i expect that my design design will run at 100 MHz before coding that in HDL.   If my design spec cannot be met, there is no reason to say that it will run if the FPGA MAX freq is greater than design freq. What will be the case when i am going for an ASIC.  Regards  freak

[Altera_Forum]

Technically, you don't know until you're done. But you should be able to get a fairly good idea early on. Your performance is going to be based mainly on levels of logic, i.e. how much logic you do between registers. If you're not going super-fast(and I won't put a number to what that means, as it varies by family, speed grade, etc.), then you usually have quite a bit of logic to work with. What often happens is user's code something, it doesn't meet timing, and then they have to pipeline it(add registers along the critical path) in order to get it to meet timing. There's also dealing with placement, which has a big affect on timing. 

Note that a LOT of large designs at large companies do not make timing all the time. These are designs from engineers who have tons of experience, but since the performance is usually driven more be a spec than by what the FPGA can do, they recode, redesign, and almost always get somethig to work.  And this isn't different than many other things. ASICs work the same way, just with a different threshold of super-fast. If you write some code for a processor, you usually don't know if it will meet your performance requirements(not Fmax, but system throughput) until testing it out. As you do more and get into this system, you'll quickly get more comfortable, but on a new design that you haven't done before, and if you haven't done a lot of FPGAs, you're just going to have to wade in and see what happens.

[Altera_Forum]

--- Quote Start ---  FPGA data sheet tells only the max operating freq of that device  --- Quote End ---   I don't agree. If you see e. g. table 5–15. cyclone ii performance from Cyclone II Device Handbook, it tells a lot more. Other interesting parameters are maximum operating frequency for particular interfaces. Also verified performance data of IP cores can give valuable hints. I can tell that I made predictions of design performance from such information more than once and it basically came true.

[Altera_Forum]

Crawl. walk, run. 

 There is no faster way.

[Altera_Forum]

Hi .. 

  Can you please tell me a little more about levels of logic. Suppose i am going to make a IP core, how can i know the levels of logic in my design.   I think by levels of logic Rysc meant Data path between two registers. If that is true, how will a designer know the data path between registers when the design has not yet started.  Regards freak

[Altera_Forum]

You don't. You start coding and you run timing analysis. If you have paths that don't meet timing, then you look at how much combinatorial logic you're cramming between registers and try to fix it(there are Quartus settings that can help, look at the Tools -> Advisors -> Timing Optimization Advisor to get started). Even if you're always making timing, run timing analysis now and then and look at your critical paths. You'll quickly develop a sense of how much logic your coding and how fast it runs. It won't be exact, but you should develop a pretty good feel. The bottom line is you're going to have to dive in, start coding, and see where it goes.

[Altera_Forum]

A few years ago, I wanted to make a pair of dressers for my house. 

I drew up the plan. I bought the wood. I checked all my theoritical calculation twice just like I was suposed to.  Then I stood before the table saw, and I stared at the wood, afraid to make a cut until I "understood" all that I wanted to know about cutting the wood.  What if the blade grabs the wood, What if I push to fast and burn the wood, what if ....  Eventually my friend (whos garage and tools I was using) came in and asked why I had not started yet. (He knew I was an Engineer and took my time triple checking everything).  We talk some more. Eventually we turned the table saw on and I just had to learn the feel of the wood going past the blade. Sometimes it was easy, other times it was hard, and I learned to adjust my "coding style" (pressure) to match the grain of the wood.  Sure, I burned the wood a few times, but in the end, I have two beautiful (in my eyes) 4 drawer dressers that I will pass on to my kids.  Just start coding and it will all work out in the end.   (Levels of logic - the is the amount of Boolean gates between registers. It does not matter if it is in the data path or the control path. It is the result of the synthesis tools "creating logic" based on your HDL code.  Many things can effect the levels of logic.  The quality of the synthesis tool.  The ability of the synthesis tool to know the target part and apply understanding of the delays in the logic( physical synthesis-time delays).  The width of the inputs in the boolean blocks of the target part (3-4-5-6-7-8 input LUTs). ) Enjoy