Auto-sensing voltage level shifters

Altera_Forum · ‎03-31-2008

I need to connect some 5V logic to FPGA devices that are not 5V tolerant. I checked different possibilites and found those "newer" auto-sensing dual-rail transcievers.

Somebody have any experience using those auto-sensing voltage translators? They seem ideal to FPGA development. No direction pin(s) needed, direction can be mixed across pins and bus contention is completely avoided.

My main concern is the sensitivity to noise of these translators, because I plan to connect them with the FPGA across a cable (using a daughterboard).

Altera_Forum · ‎03-31-2008

As the said transceivers (as far as I know, you should tell the intended type to allow a specific check) are basically switches with voltage limiting characteristic, they won't improve noise margin. Also the drive current must be delivered by the primary source. I think that a chance to repeat a signal should be used to improve signal quality, particularly with cables. For longer distance interfaces, I would try to use differential signaling where possible.

Altera_Forum · ‎03-31-2008

Hi FvM,

Thanks for your quick reply.

No, they are not bus switches. They are dual-supply fully buffered. Seems to me you are not aware about these automatic voltage translators. They are rather new, I think.

Please check, i.e, : http://focus.ti.com/docs/prod/folders/print/txb0108.html

Altera_Forum · ‎03-31-2008

Be carefull with these, they don't look like ordanary buffers.

1. check the logic levels, its not TTL

2. they can not drive a lot of current (in the sense of a normal bus driver that does 20 - 40 mAmps). Look to the description of the working principle and schematic diagram at the end of the datasheet.

Stefaan

Altera_Forum · ‎03-31-2008

I admit, that the said devices look interesting, they are different from the bidirectional switch type that I know e. g. from Maxim. However, I'm unable to foresee their behaviour in different applications, I'll evaluate it occasionally. The device at least isolates the load from FPGA and also is able to protect sensitive FPGA inputs against voltage transients and overshoots as a usual buffer does.