birectional port

Altera_Forum · ‎04-01-2008

for the simulation the output data correctly appears on the BIDIR[x]~result lines but it doesn't appear on the regular BIDIR[x] lines. is this normal? is there a way to combine the 8 BIDIR[x]~result lines so that they appear as one bus line instead of 8 single lines ?

http://img267.imageshack.us/img267/8416/bidirbs1.png

library ieee;
use ieee.std_logic_1164.all;
entity bidirection is
port (
      E     : in std_logic;
      BIDIR    : inout std_logic_vector(7 downto 0)
      );
end bidirection;
architecture behaviour of bidirection is
signal A : std_logic_vector(7 downto 0) := "11110000";
begin
process(E)
begin
if(E = '0') then
	BIDIR <= A;
else
	BIDIR <= "ZZZZZZZZ";
end if;
end process;
end behaviour;

Altera_Forum · ‎04-01-2008

The simulate result for bidirectinal pin is always showed in bipin~result. You can select all the *~result signals and click right mouse button and then select group to combine those signals.

Altera_Forum · ‎04-01-2008

This is simply how the the waveform viewer works. The original pin entry FOO allows you to specify the external value being driven onto the bidirectional pin but the FOO~result pin shows you the actual value on the pad, which could be the external or internal value, depending on who's driving the pad at any given moment in time.