How to route output clock of alt2gxb to a pll?

[Altera_Forum]

Hi, 

The error information is "Error: Clock input port inclk[0] of PLL "pllo:u_pllo|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info: Input port INCLK[0] of node "pllo:u_pllo|altpll:altpll_component|pll" is driven by siigx125_phyx1:phy|altpcie_serdes_2sgx_1x125:phypcsx1|alt2gxb:alt2gxb_component|rx_coreclk_in[0] which is CLKOUT output port of HSSI_TRANS type node"  I'd like to create additional x1 and x(1/2) in-phase clock based on alt2gxb:clk. Thus, alt2gxb:clk is connected to a altpll module. But it caused above error.  Please help.  Jimmy

[Altera_Forum]

Hello, 

 The siigx handbook says, in the volume-2 page 7-73, "An internally generated global signal cannot drive the PLL". The clock output from the alt2gxb is always routed through global signal, so you can't do this.

[Altera_Forum]

Thanks for reply. 

Its my first time to run altera fpga. do you have any suggestions about my requirement?  best regards, Jimmy note, I try to output gxb clock outside fpga chip and connect it back to a clock pin , then  atlpll can generate x1 and x(1/2) in-phase clock. But timing between gxb:clk and pll:x1/x(1/2) clock cannot be check exactly.

[Altera_Forum]

Hi, 

 I don't know if it meets your requirement, but the only way I can figure out is to use phase comp fifo in the gxb like handbook vol-2 page 2-131. I attached the sample.  Thanks!