instantiating RAM and multiple instances

[Altera_Forum]

hi, Im new here and new to fpgas, verilog and quartus but learning fast. 

 I have a question...  I have written a program which requires data to be buffered from two ADCs.  I have foudn an example program which does it but only on one channel. Can I write two instantiations for the same files to make/use two ram blocks or do I need to create another RAM block?  Also If I wanted to create one and use it in my program how do I include it in my verilog design file library. Do I need to go to a menu and include the file so it knows where it is?  Ive been trying to find this for a while but not sure what to search for and what to look at. Learning that it was called instantiateing was a big help. The syntax is my biggest issue I think.  Regards Robin

[Altera_Forum]

A Megawizard generated RAM module can be instantiated as often as you like, up to the RAM capacity. By creating the module through Megawizard, the designfile is automaticly added to your project. Also a file with component definition for the module and an instantiation template file are created. You only need to copy the content of the two files to the design file, that shall use the RAM. 

 You will notice, that you may skip one level and instantiate altsyncram directly in your design. You can use the code from the Megawizard generated file as a template. This would allow to have modified copies of the original RAM module without using the Megawizard, or e. g. parameterizable modules that directly derive altsyncram instance parameters from module parameters.  Alternatively, you can "infer" RAM directly from HDL code, without explicitely instantiating altsyncram. Quartus II software manual has examples how to in Quartus integrated synthesis chapter. But this technique doesn't work for all RAM types, e. g. for dualport RAM, you need altsyncram.

[Altera_Forum]

Thankyou for that I think I understand but Im still not quite sure, I have a ram file for a dual port RAM which has been modified and is not produceable directly by the wizard. Until I learn more about this I would like to generate two of these. Can I create an instatiate code block which uses this file to make several 512 byte dual port RAM blocks in the FPGA? If not do I need to modify the originals and save again as another file name? 

 Thankyou ever dso much for a swift reply and help its appreciated.  Robin

[Altera_Forum]

A module can have multiple instances. I previously overlooked that you said to use verilog, so a component definition isn't needed. But a verilog module instance as a VHDL component instance always has an module indentifier, that references the name of the module and an arbitrary instance identifier. For a RAM it's the same as for a simple logic gate (from an Verilog Tutorial): 

nand2 n1(in1, in2, out1); nand2 n2(in3, in4, out2);