The efficiency of DDR and DDR2 SDRAM High-Performance Controller

[Altera_Forum]

Hi, everyone! 

Have anybody used Altera's DDR and DDR2 SDRAM High-Performance Controller in Cyclone 3?What do you think of the efficiency of this controller?  I think the efficiency won't be high.The controller does not support additive latency.When launced four write operation in the local interface consecutively,then the four operation are not implemented consecutively in the memory interface,there are gaps on the dq bus.This happened even when the four operation are in the same col, the same row and the same bank.As the controller only support a burst length of 4,there will be a gap(1 clk) every 4 beats(2clk) of data on the dq bus.So that is to say the controller has a max efficiency of 66.7%(2/3).:eek:   What is your opinion?

[Altera_Forum]

I was testing DDR2 HP controller with Arria GX and it performed continuous read or writes within a column (except for intermediate refresh cycles). So I think it could be a problem of how the controller is handled at the interface. I don't see a reason, why Arria GX should behave different from Cyclone III.

[Altera_Forum]

What Avalon master are you using to test this? Is it a custom master logic or Altera's? 

 Be aware that the Nios processor master is not fully latency aware, at least in my tests (if you are using a Nios to test this).  A DMA type master with proper latency aware logic will achieve 100% same-row efficiency, in between consecutive refreshes of course.