Clock skews, enables and timing

[Altera_Forum]

Can someone help me? 

I am new to this and have been learning from scratch to program FPGAS and windows at the same time whilst building hardware.  I have written some code for a data capture system which works mostly but has timing errors.  When I look at the compile window it gives me errors such as gated clocks causing skew plus timing for slow model unable to be met plus clock signal reg bit 0 used as biffer plus a few others.  I am not sure how to go about sourcing the problems and fixing and its taken me every minute I have for 4 months to get where I have got. Im on a tight time scale as I want to use this project on holiday in a couple of months and have a lot to do. This is the only bit Im utterly stuck on.  Someone mentioned on here that I need to use chip enable clocks to sort out the gated clock issue but I do not know how to do this?  could someone give me some pointers in verilog? Also if I post the errors could we explain what they mean?  As I said the program works it just shifts the data back and forward in timing instead of capturing it all at the same time as I would expect. Its not a very big program so cant be much wrong allthough it is messy for a first verilog programming attempt.  Yours hopefully Robin Burrows

[Altera_Forum]

--- Quote Start ---  Can someone help me? Someone mentioned on here that I need to use chip enable clocks to sort out the gated clock issue but I do not know how to do this?   --- Quote End ---   instead of passing a clock through a gate i.e. AND'd with some other signal you want to gate the clock with, feed the clock as normal into the clk inputs of the register(s) which follow i.e. are currently fed by your gated clock and then feed the gate signal into the clock enable (clken) input of the very same registers.

[Altera_Forum]

My code is below. It tells me that: 

 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  Info: Detected ripple clock "TriggerFish~reg0" as buffer  Info: Detected ripple clock "samplefreq~reg0" as buffer  Im still trying to understand the issues but understand better thanks  // Set fish trigger settings assign Reset = !ResetA; assign LED = TriggerFish;  // Set fish trigger settings always @(posedge clk or posedge Reset) begin  if (Reset) begin  triggerCnt <= 0;  end  else if (!Reset) begin  if (resetTriggerCnt) begin  triggerCnt <= 0;  end  else begin  triggerCnt <= triggerCnt + 1;  end  end end  always @(posedge clk or posedge Reset) begin  if (Reset) begin  TriggerFish <= 0;  end  else if (triggerCnt == 23500000) begin // Trigger fish space duration   TriggerFish <= 1;  end   else if (resetTriggerCnt) begin  TriggerFish <= 0;  end end  always @(posedge clk or posedge Reset) begin  if (Reset) begin  resetTriggerCnt <= 0;  end  else if (triggerCnt == 24000000) begin // Trigger fish space duration  resetTriggerCnt <= 1;  end   else begin  resetTriggerCnt <= 0;  end end  // new code added 07/03/08------------- always@(posedge clk) begin if(Reset)  begin  samplefreqcount=0;  samplefreq=0;  end  else  if(samplefreqcount==363)// Here we put half of  //available clk  begin  samplefreq=~samplefreq;  samplefreqcount=0;  end    else  samplefreqcount = samplefreqcount + 1; end

[Altera_Forum]

Do you have any special reason to use blocking assignment for "samplefreq" and "samplefreqcount"? 

 # samplefreq=~samplefreq; # samplefreqcount=0; instead of # samplefreq<=~samplefreq; # samplefreqcount<=0;

[Altera_Forum]

Im not sure what block assignments mean I just had a go at writing this to learn. There is alot more but I havent posted it yet. 

 Can someone explain the block thing and also if there are any problems with this bit of the code.  Regards Robin

[Altera_Forum]

Hello, 

 With the second thought I find the blocking assignments are no harm with synthesis, but it may cause simulation issue. So I recommend you to use "<=" instead of "=" in the always.

[Altera_Forum]

--- Quote Start ---  When I look at the compile window it gives me errors such as gated clocks causing skew...  Someone mentioned on here that I need to use chip enable clocks to sort out the gated clock issue but I do not know how to do this?  could someone give me some pointers in verilog?  --- Quote End ---     See http://www.alteraforum.com/forum/showthread.php?t=2388. That thread goes into detail about design recommendations for gated clocks. One of the posts talks about clock enables and has a reference to the Quartus text editor templates showing the proper way to code for clock enables.