HSMC Pinout on Stratix II

[Altera_Forum]

Hi, 

 I am using a PCIe Stratix II dev kit. I am a little confused about the hsmc pinouts from the fpga. For example one of the pins I want to use is hsma_tx_d_p[0]...  First question is that there's another pin hsma_tx_d_n[0].. Does this mean that for each signal pin I use, I have to provide a return path i.e. I have to tie both p[0] and n[0] pins  Second question is what does the 'd' stands for because there are other pins labeled hsma_tx__p[0], so I am not sure if digital makes sense  The last question is which one of the clock signals from the fpga to hsmc is the 100 Mhz clock?  I have looked over the HSMC spec sheet and the dev kit spec/manual but didn;t find any satifactory answers.  I appologize if I have too many questions in the same post and if these questions sound stupid. Any help wioll be appreciated.  Thanks ini advance.

[Altera_Forum]

The HSMC signal names sounds almost self-explananatory to me, also without knowing a specification. You have single-ended data lines and line pairs intended for differential signals. The latter are connected to Stratix I/O pins capable of LVDS differential IO, Rx or Tx respectively. Other lines are intended as clocks, connected to dedicated clock FPGA pins. 

 As with all designs, the actual usage of the signals depends on your design. E.g., if you want to use LVDS Tx from FPGA, you are restricted to dedicated FPGA pins, otherwise you can use these pins as you like. Then the p and n designators wouldn't mean a thing.

[Altera_Forum]

Thanks, 

 That makes sense. The only thing I am still not clear on is that that does any of the clock lines provide the 100 Mhz clock and is it possible to program (in software) the fpga to provide a clock of say 25 Mhz or 50 Mhz on clock lines.

[Altera_Forum]

The HSMC connector pin mapping to FPGA pins is included in the board manual, may be it's also included in example designs. From the pin mapping, you identify, that e. g. hsma_rx_n and _p pins are GXB pins, while hsma_d_rx_n and _p are LVDS-pins, that can be used as single ended I/O also. You can also identify, that hsma_clk_out0 is a PLL11 output intended as single-ended clock, while hsma_clk_out_n and _p are LVDS outputs but not dedicated clock outputs. So hsma_clk_out0 should be used, if a dedicated clock output is required, but the 100 MHz clock present at the port can be routed to any I/O pin with reduced timing accuracy.

[Altera_Forum]

Thanks, 

 Really appreciate it. This cleared some of the cobwebs.