clk & i/o assignment on FPGA Board

[Altera_Forum]

I am testing my chip design using Apex Nios 2 board. However, my design was not done based on it. Hence, I would like to know: 

1. How to connect an external clock input (from crystal) to a FPGA Board 2. How to connect i/o signals with FPGA Board  I planned to utilize the 3.3V Expansion Prototype Connector. Is this the correct way? Is there any document that describe such "non-standard" usage of the i/o pins for Apex Nios 2?  This is the 1st time I using a FPGA Board, sorry if I can't describe the problem well.

[Altera_Forum]

--- Quote Start ---  I am testing my chip design using Apex Nios 2 board. However, my design was not done based on it. Hence, I would like to know: 1. How to connect an external clock input (from crystal) to a FPGA Board 2. How to connect i/o signals with FPGA Board   I planned to utilize the 3.3V Expansion Prototype Connector. Is this the correct way? Is there any document that describe such "non-standard" usage of the i/o pins for Apex Nios 2?   This is the 1st time I using a FPGA Board, sorry if I can't describe the problem well.  --- Quote End ---     It appears that you want to communicate with your board with signals originating from outside the board. Can you write what kind of I/O interfaces your board has? For example, if it has interfaces like RS-422, then you can route your signals including the clock through this interface.