I2S and FIR Compiler

Altera_Forum · ‎07-02-2008

Hi everyone,

I have to design an interpolation filter which will work as a cascade of three filters:

1. Inverse - sinc filter which compensates for droop from CIC filter (interpolation x2)

2. Halfband filter (interpolation x2)

3. CIC filter (interpolation x32)

Overall interpolation factor is 128. Then signal from this cascade will be send to 5th order 1bit sigma-delta modulator and then this one-bit data stream will be send to an audio output on Altera LiveDesign Eval Board -> livedesign cyclone ep1c12f324c8 (http://www.proto-labs.com/foto/altium_alt_tn.jpg)

Input signal is going from CS8416 192 kHz Digital Audio Receiver in I2S format:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/0i2s.png

I have connected some signals from CS8416 to I/O pins on Altera board:

1. SDOUT - serial input data to interpolation filter

2. OLRCK - Fs = 44100 Hz

3. OSCLK - bit clock = 64*Fs

4. RMCK - 128*Fs

This signal goes to "Deserializer" module (see code below):

module i2s_rx(      input osclk,
                     input reset,
                    input lrck,
                    input sdin,
                    output reg  rx_data,
                    output reg rx_ready ); 
                    
reg  shiftreg = 0;
reg lrck_prev = 0;
always@(posedge osclk or negedge reset) begin
   if(!reset) begin
      lrck_prev<=0;
      shiftreg<=0; 
       
   end else begin
   
   if(lrck) shiftreg <= {shiftreg, sdin};
   
   if((lrck_prev) & (!lrck)) begin
      rx_ready<=1; 
      rx_data<=shiftreg;
  end
      else rx_ready<=0; 
      
   lrck_prev<=lrck;
   end
end
endmodule

Block schematic of input section looks like this:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/03.png

My base clock is that RMCK = 128*Fs from CS8416. I use 7bit counter to divide this clock and get count[6] (44100) for synchronize data from i2s_rx module with that clock.

And now it starts to be problem...

In addition to FIR Compiler timing diagrams:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/015.png

I must drive FIR Compiler with two "clocks". For interpolation x2 it will be:

count[5](88200Hz) -> CLK

count[6](44100Hz) -> SINK_VALID

Other signals to FIR Compiler are connected as follows:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/04.png

Altera_Forum · ‎07-02-2008

In timing simulation, in my opinion, it works:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/01.png

This i2s_rx takes only 16 bits from one channel (when OLRCK is high).

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/02.png

In simulation I feed serial_data_in with random values with f = 64*Fs. Module i2s_rx takes only first 16 bits. Data is synchronized with RMCK/128 = 44100 Hz and then go to filter.

FIR is parametrized with these values:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/014.png

When I program device and feed CS8416 with 16bit, 44100Fs sinus I get very distorted sinus on output of the board. When I change freq of sinus I hear this change in audio but for sure - this isn't working good. Morover, when I change something in input signal (amplitude or frequency) leds on board are flashing (they are not assigned).

Morover I get known warnings about clocks, I have assigned them in that way:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/05.png

Altera_Forum · ‎07-02-2008

but I get Clock Hold on RMCK:

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/06.png

http://www.fullinstrumentale.neostrada.pl/Altera_mail/Mail_to_Altera/07.png

For sure, I have made couple of mistakes and that's the reason why I write to You.

1. Is that a problem with that I'am not using on-board clock (50MHz)?

2. Does FIR Compiler is configured and placed correct?

3. How can I get rid of those Clock Holds? That would be a problem (I assigned count[6] and count[5] to I/O pins and I checked that they act in the same way as in timing simulation) ?

Best regards and I hope someone will help me :)

Marcin Lewandowski