5 V in and out

[Altera_Forum]

Now my little project is almost finished. The last problem is how to get 5 V out from the board (Terasic micro kit). The board is connected to USB port and it outputs 3.3 V. But I want to read signals of 5 V and also write 5 V. There's two pins that say 5V. Should I just supply 5 V to these pins and keep USB connected? If so, why's there eight 3.3V pins?

[Altera_Forum]

MAX II has no 5V-tolerant I/Os. Please consult the MAX II device manual to learn about supported I/O standards, particularly the multivolt i/o interface chapter. The most simple variant is to use a series resistor and enable the PCI clamp diodes, which are available for the Bank 3 I/O-pins. But 5V input should be applied then in configured state of MAX II only. Or use level translators.

[Altera_Forum]

What is that PCI clamp diode? I read the following about multi-voltage systems:  

 "To make MAX II device outputs compatible with 5.0-V CMOS devices, configure the output pins as open-drain pins with the PCI clamp diode enabled, and use an external pull-up resistor."  "MAX II devices can interface with 5.0-V devices by slightly modifying the external hardware interface and enabling PCI clamping diodes via the Quartus II software."  And what is open-drain pin? How to enable PCI clamping diode? Sorry my newbie questions...  This is from Quartus Help: "MAX II devices have a device-wide output enable (DEV_OE) to control the output enable for every output pin in the design and an internal PCI clamp diode, which can make the device 5.0-V tolerant with the use of an external resistor."

[Altera_Forum]

I'm pretty sure, that all requested information can be found in the MAX II device handbook and Quartus documentation. Cause the documents are rather extensive, it may be not always easy to find. But it's always useful to read the handbooks thoroughly to my opinion. If you're looking for a particular detail, an Acrobat text search can help. 

 Open drain outputs can achieve an output voltage above 3.3V VCCIO, e. g. 4.0V, but with slow rising edge only. If your connected 5V peripheral is satified with 3.3V output voltage (e. g. when using HCT logic rather than HC), the regular LVTTL or LVCMOS I/O standard can be used on output from MAX II. On input, the logic level has to be reduced. PCI diodes with a series resistor are one possible option, a two resistor voltage divider is another. PCI diodes can be enabled in Quartus Pin Planner (use the context menu to display the respective columns) or Assignment Editor.