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hello,
I want to use a signal for the clock input of a pll. This signal comes from the CDR of the embedded transceiver in the FPGA. The error messages say that I can only drive the pll-input with a global clock or a IO-Pin. Can I make any assignments to define this signal as a clock? Thanks very much.Link Copied
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If you do not send the signal to a general PLL input, but rather JUST to a global clock line in the FPGA, you should be able to do that in the assignment editor.
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