DE2 PLL Phase Shift Problem, Pase Shifting is not viewable

[Altera_Forum]

Hey People, I have been using the DE2 board for a while now with the nios processors and my own designs. 

I was wondering if anyone could help me with this PLL Problem. I have a one PLL with 3 stepped up outputs (c2 .. 0) at 200 MhZ each. I want a pase shift to be present on each and have done so in the megafunctions wizard and this is its output. http://img137.imageshack.us/img137/875/altpll0wave0du9.jpg    I have since divided this down and tried to view any phase shift in the (c2 .. 0) on my CRO and there is none, i then divided it down further and connected the outputs to some LED's on the DE2 Board (Divided down to 0.5Hz or once every 2 Seconds) so i could see if there was any and if my CRO was stuffed. Yet this was not successfull Does anyone have any suggestions or can tell me what i am doing wrong. To divide the clock i am using D-FlipFlops In the Simulator it simulates fine in functional, and the timing analysis dows show the phase shift. I am using the Quartus II v6.1 Free Web Edition. The project compiles with no errors and 7 warnings as follows. Here is an example of the PLL and D-FF that i am using to divide the clock in a Daisy Chain Config http://img237.imageshack.us/img237/7996/setupzx0.jpg    Here are the warning messages from compilation.   Warning: Using design file /altpll0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: altpll0-SYN Info: Found entity 1: altpll0 Warning: Output pins are stuck at VCC or GND Warning: Pin "Control" stuck at VCC Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings Info: Allocated 136 megabytes of memory during processing Info: Processing ended: Mon Jul 14 21:09:42 2008 Info: Elapsed time: 00:00:02 Info: ******************************************************************* Info: Running Quartus II Partition Merge Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition Info: Processing started: Mon Jul 14 21:09:44 2008 Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off KLR -c KLR --merge=on Info: Using synthesis netlist for partition "Top" Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings Info: Allocated 95 megabytes of memory during processing Info: Processing ended: Mon Jul 14 21:09:44 2008 Info: Elapsed time: 00:00:00 Info: ******************************************************************* Warning: Found 7 output pins without output pin load capacitance assignment Info: Pin "COut2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Control" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "COut1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "COut0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Test_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Test_2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Test_3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin Control has VCC driving its datain port Info: Quartus II Fitter was successful. 0 errors, 2 warnings Info: Allocated 222 megabytes of memory during processing Info: Processing ended: Mon Jul 14 21:10:03 2008 Info: Elapsed time: 00:00:18 Info: Quartus II Assembler was successful. 0 errors, 0 warnings Info: Allocated 176 megabytes of memory during processing Info: Processing ended: Mon Jul 14 21:10:21 2008 Info: Elapsed time: 00:00:16 Info: ******************************************************************* Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled Warning: Found 84 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "inst15" as buffer Info: Detected ripple clock "inst17" as buffer Info: Detected ripple clock "inst30" as buffer   **** .... More Lines Like this .... **** Info: Detected ripple clock "inst555" as buffer Info: Detected ripple clock "inst556" as buffer Info: Detected ripple clock "inst557" as buffer Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings Info: Allocated 102 megabytes of memory during processing Info: Processing ended: Mon Jul 14 21:10:23 2008 Info: Elapsed time: 00:00:01 Info: Quartus II Full Compilation was successful. 0 errors, 7 warnings

[Altera_Forum]

The warnings aren't related to PLL operation in general, they can be ignored regarding phase shift.  

 I would expect, that the phase shift is implemented as shown in the schematic symbol, however, the actual PLL parameters can be reviewed in compilation report under fitter/ resource section/PLL. I can't see how the phase shift can be vizualized by dividing the clock, cause this operation doesn't increase the ns scale of the phase shift. But it would be detectable with a fast multichannel oscilloscope.

[Altera_Forum]

Hmm, thanks for the tip. I have an idea how to test it, Ill let you know what i find. 

 as for my CRO it is capable of seeing the phase shifts i am trying to acheive.   regards RSTEP